• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1991.11a
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• pp.19-29
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• 1991

본 논문에서는 관용 암호시스템의 세션키이분배방법으로 매우 효율적이며 안전한 새로운 키이분배 시스템을 제안한다. 제안된 시스템은 한번 혹은 두번의 모듈라 멱승 연산만으로 세견키이 공유가 가능하므로 기존의 어떤 방식보다도 효율적이라 할 수 있다. 또한 알려진 어떤 공격에 의해서도 세견키이를 불법 계산하는 것이 불가능함을 보일 수 있으므로 안전성을 확보할 수 있다는 장점도 지닌다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.676-678
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• 2003

최근에 2.5G나 3G 이동 단말 장치를 위한 프로세서로, 다양한 멀티미디어가 가미된 응용구현이 가능하도록 RISC 프로세서와 DSP를 포함하는 단일 칩 프로세서 기술이 등장하고 있다. 이에 따라 듀얼 프로세서 구조에서 비디오 인코딩/디코딩의 처리 속도를 향상시키기 위안 비디오의 인코더/디코더 구조를 제안한다. 기존의 연구에서는 비디오의 인코딩/디코딩의 전 과정을 DSP가 담당하도록 설계하였으나 많은 비트 연산이 필요한 부분에서는 RISC 칩보다 효율성이 낮게 된다. 이러한 문제점을 해결하기 위하여 본 논문에서는 비디오 신호 처리의 인코딩/디코딩을 구성하는 모듈들을 DSP와 RISC의 특성에 맞도록 분리해 수행시킴으로써 효율성을 높이고자 한다.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.65-68
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• 2004

일회용 대리 서명은 원 서명자를 대신한 정당한 대리 서명자가 메시지에 대한 서명을 오직 한번만 수행하는 기법으로 Huaxiong와 Josef(HJ)는 일방향 해쉬 함수를 이용한 일회용 대리 서명 기법을 제안하였다[1]. HJ 방식은 공개키 암호 방식에 비해 상대적으로 연산속도가 빠르며 효율적이지만, 원 서명자는 사전에 많은 비밀키/공개키 쌍을 생성해야 하고, OT(Oblivious Transfer) 프로토콜[2,3]을 사용함으로 추가적인 계산량의 문제가 발생한다. 따라서 본 논문에서는 HJ 방식의 일회용 대리 서명 방식의 문제점을 지적하고, 이를 개선한 효율적 일회용 대리 서명을 제안한다.

• Annual Conference of KIPS
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• 2008.11a
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• pp.774-777
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• 2008

지리정보는 여러 분야에서 활용되고 그 데이터 양도 방대하여 효율적으로 저장하여 관리해야 할 필요가 있다. 본 논문은 균등 분할 방식과 비균등분할 방식에 의한 두 가지 지리정보 표현 및 압축방법을 수행하는 연산회수와 자료의 효율성 등을 중심으로 비교하였다. 두 가지 방법 모두 효율적인 활용이 가능하며 상황에 따라 기본 방법에서 수정을 가하여 사용할 수도 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of KIISE:Databases
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• v.33 no.6
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• pp.620-630
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• 2006

Event-detection is an important application of sensor networks. Join operations can facilitate event-detection with a condition table predefined by a user. When join operations are used for event-detection, it is desirable, if possible, to do in-network join processing to reduce communication costs. In this paper, we propose an energy-efficient in-network join algorithm, called PBA. In PBA, each partition of a condition table is stored along the path from each node to the base station, and then in-network joins are performed on the path. Since each node can identify the parts to store in its storage by its level, PBA reduces the cost of disseminating a condition table considerably Moreover, while the existing method does not work well when the ratio of the size of the condition table to the density of the network is a little bit large, our proposed method PBA does not have such a restriction and works efficiently in most cases. The results of experiments show that PBA is efficient usually and especially provides significant cost reduction over existing one when a condition table is relatively large in comparison with the density of the network, or the routing tree of the network is high.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.3
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• pp.70-79
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• 2007

H.264/AVC has many repeated computation for motion estimation. Because of that, it takes much time to encode and it is very hard to implement into a real-time encoder. Many fast algorithms were proposed to reduce computation time but encoding quality couldn't be qualified. In this paper we proposed a new motion vector prediction method for efficient and fast full search H.264/AVC motion estimation. We proposed independent motion vector prediction and SAD share for motion estimation. Using our algorithm, motion estimation reduce calculation complexity 80% and less distortion of image (less PSNR drop) than previous full search scheme. We simulated our proposed method. Maximum Y PSNR drop is about 0.04 dB and average bit increasing is about 0.6%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.3
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• pp.167-170
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• 2018

The method of moments(MoM) is one of the most popular integral-equation-based full-wave simulation methods, and the multi-level fast multipole method(MLFMM) algorithm can be used for its efficient calculation. When calculating the surface current on the large scatterer in the MoM or MLFMM, iterative methods for the final matrix inversion are used. Among them, BiCGstab(l) has been widely adopted due to its good convergence rate. The number of iterations can be reduced when l becomes larger, but the number of operations per iteration is increased. Herein, we analyze the computational complexity of BiCGstab(l) in the MLFMM method and propose an optimum choice of l.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.409-416
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• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.