• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.3
• /
• pp.134-142
• /
• 2002

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The window operation is one of important geometry operations in image processing, which extracts a sub-image indicated by a window in the image. In this paper, we present an algorithm to perform the window operation of binary images represented by quadtrees, using three-dimensional $n{\times}n{\times}n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of $n{\times}n{\times}n$ RMESH.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.16 no.4
• /
• pp.83-89
• /
• 2006

In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in GF($2^m$). In this paper, we propose a new, simpler, parallel multiplier over GF($2^m$) having a type II optimal normal basis, which performs multiplication over GF($2^m$) in the extension field GF($2^{2m}$). The time and area complexity of the proposed multiplier is same as the best of known type II optimal normal basis parallel multiplier.

• Journal of Korea Game Society
• /
• v.13 no.6
• /
• pp.43-52
• /
• 2013

Path finder is one of the very important algorithm of artificial intelligence and is a process generally used in many game fields. Path finder requires many calculation, so it exerts enormous influences on performances. To solve this, many researches on the ways to reduce the amount of calculate operations have been made, and the typical example is A* algorithm but it has unnecessary computing process, reducing efficiency. In this paper, to reduce the amount of calculate operations such as node search with costly arithmetic operations, we proposes the weight based pre-processing A* algorithm. The simulation was materialized to measure the efficiency of the weight based pre-process A* algorithm, and the results of the experiments showed that the weight based method was approximately 1~2 times more efficient than the general methods.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.04b
• /
• pp.131-133
• /
• 2000

이 논문에서는 다차원 색인 구조에서 질의를 지연시키는 주된 요인인 노드 분할연산과 MBR(Minimun Bounding Regions)변경 연산에 대해 효율적으로 대처하는 동시성 제어 기법을 제안한다. 분할 시 탐색이 지연되는 시간을 최소화 하기 위해 대부분의 과정에서 질의와 호환되는 공유 래치를 획득한 후 수행하고 분할이 발생된 노드에 엔트리들이 복사되는 동안만 배타 래치를 획득하는 방법을 사용한다. MBR 변경 연산의 동시성을 높이기 위해 부분적인 잠금 결합을 사용한다. 즉, MBR 변경 연산중 주로 발생되는 MBR이 증가되는 삽입연산은 잠금 결합을 수행하지 않고, 감소되는 삭제 연산만 잠금 결합을 수행한다. 또한 성능 평가를 통하여 제안된 동시성 제어 기법이 GiST의 동시성 제어 알고리즘에 비해 처리율 관점에서 성능이 우수함을 보인다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2007.06b
• /
• pp.401-405
• /
• 2007

본 논문은 임베디드 시스템에서 효율적인 파일 연산을 위한 메타 데이터의 구조와 파일 연산 최적화 기법을 제안한다. 플래시 메모리는 비휘발성이며 크기가 작고 전력소모도 적으며 내구성이 높아 임베디드 시스템에 널리 사용되고 있다. 하지만 제자리 덮어쓰기 (update-in-place)가 불가능하고 메모리 셀에 대한 초기화 횟수가 제한되어 있으며 바이트 단위의 입출력이 불가능하다. 이러한 하드웨어적 특성 때문에 NAND 플래시 메모리 전용 파일 시스템으로 YAFFS(Yet Another Flash File System)가 개발 되었지만 비효율적인 파일연산 과정의 문제가 존재한다. 본 논문은 YAFFS의 파일 연산을 분석하여 이를 개선시켜 파일 연산 최적화 기법을 제시하고, YAFFS에 적용하여 성능 평가를 한다.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.5
• /
• pp.634-644
• /
• 1995

In this paper, we propose a mechanism to transform more effective and semantically equivalent queries by using appropriately represented three kinds of knowledge. Also we proposed a mechanism which transforms partially omitted components or expressions into complete queries so that users can use more simple queries. The knowledges used to transform and optimize are semantic, structural and domain knowledge. Semantic knowledge includes semantic integrity constraints and domain integrity constraints. Structural knowledge represents physical relationship between relations. And domain knowledge maintains the domain information of attributes. The proposed system optimizes to more effective queries by eliminating/adding/replacing unnecessary or redundant restrictions/joins.

• Review of KIISC
• /
• v.16 no.1
• /
• pp.112-116
• /
• 2006

현대의 디지털통신기기나, 오디오/비데오 전자기기엔 항상 비바이나리 에러정정복부호기가 사용되는데 그중 필수적으로 사용되는 Reed Solomon복부호화기기를 설계할 때, 갈로이스장 내의 원소간 연산이 필수적으로 사용된다. 본논문에선 이 연산장치를 쉽고 빠르게 구현할 수 있는 효율적 설계법을 제시한다. 또한각 연산기에 대해 예를 들어 설명하고 증명했다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.778-781
• /
• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.35-42
• /
• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.6-13
• /
• 2011

Due to its robustness to illumination change, normalized cross-correlation based similarity measurement is widely used in many machine vision applications. However, its inefficient computation structure is not adequate for real-time embedded vision system. In this paper, we present an efficient hardware architecture based on a normalized cross correlation (NCC) for fast image similarity measure. The proposed architecture simplifies window-sum process of the NCC using the integral-image. Relieving the overhead to constructing integral image, we make it possible to process integral image construction at the same time that pixel sequences are inputted. Also the proposed segmented integral image method can reduce the buffer size for storing integral image data.