• Journal of KIISE:Software and Applications
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• v.37 no.12
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• pp.882-891
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• 2010

Many automated dynamic test data generation technique have been proposed. The techniques evaluate fitness of test data through executing instrumented Software Under Test (SUT) and then generate new test data based on evaluated fitness values and optimization algorithms. Previous researches and experiments have been showed that these techniques generate effective test data. However, optimization algorithms in these techniques incur much time to generate test data, which results in huge test case generation cost. In this paper, we propose a technique for reducing the time of evaluating a fitness of test data among steps of dynamic test data generation methods. We introduce the concept of Fitness Evaluation Program (FEP), derived from a path constraint of SUT. We suggest a test data generation method based on FEP and implement a test generation tool, named ConGA. We also apply ConGA to generate test cases for C programs, and evaluate efficiency of the FEP-based test case generation technique. The experiments show that the proposed technique reduces 20% of test data generation time on average.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.465-472
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• 2006

Recently, many suggestions have been made in image segmentation methods for extracting human organs or disease affected area from huge amounts of medical image datasets. However, images from some areas, such as brain, which have multiple structures with ambiruous structural borders, have limitations in their structural segmentation. To address this problem, clustering technique which classifies voxels into finite number of clusters is often employed. This, however, has its drawback, the influence from noise, which is caused from voxel by voxel operations. Therefore, applying image enhancing method to minimize the influence from noise and to make clearer image borders would allow more robust structural segmentation. This research proposes an efficient structural segmentation method by filtering based clustering to extract detail structures such as white matter, gray matter and cerebrospinal fluid from brain MR. First, coherence enhancing diffusion filtering is adopted to make clearer borders between structures and to reduce the noises in them. To the enhanced images from this process, fuzzy c-means clustering method was applied, conducting structural segmentation by assigning corresponding cluster index to the structure containing each voxel. The suggested structural segmentation method, in comparison with existing ones with clustering using Gaussian or general anisotropic diffusion filtering, showed enhanced accuracy which was determined by how much it agreed with the manual segmentation results. Moreover, by suggesting fine segmentation method on the border area with reproducible results and minimized manual task, it provides efficient diagnostic support for morphological abnormalities in brain.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of KIISE:Databases
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• v.34 no.2
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• pp.119-132
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• 2007

In molecular biology, approximate subsequence search is one of the most important operations. In this paper, we propose an accurate and efficient method for approximate subsequence search in large DNA databases. The proposed method basically adopts a binary trie as its primary structure and stores all the window subsequences extracted from a DNA sequence. For approximate subsequence search, it traverses the binary trie in a breadth-first fashion and retrieves all the matched subsequences from the traversed path within the trie by a dynamic programming technique. However, the proposed method stores only window subsequences of the pre-determined length, and thus suffers from large post-processing time in case of long query sequences. To overcome this problem, we divide a query sequence into shorter pieces, perform searching for those subsequences, and then merge their results. To verify the superiority of the proposed method, we conducted performance evaluation via a series of experiments. The results reveal that the proposed method, which requires smaller storage space, achieves 4 to 17 times improvement in performance over the suffix tree based method. Even when the length of a query sequence is large, our method is more than an order of magnitude faster than the suffix tree based method and the Smith-Waterman algorithm.

• Journal of KIISE
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• v.43 no.10
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• pp.1115-1123
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• 2016

Assumption-based truth maintenance system (ATMS) is a tool that maintains the reasoning process of inference engine. It also supports non-monotonic reasoning based on dependency-directed backtracking. Bookkeeping all the reasoning processes allows it to quickly check and retract beliefs and efficiently provide solutions for problems with large search space. However, the amount of data has been exponentially grown recently, making it impossible to use a single machine for solving large-scale problems. The maintaining process for solving such problems can lead to high computation cost due to large memory overhead. To overcome this drawback, this paper presents an approach towards incrementally maintaining the reasoning process of inference engine on cluster using Spark. It maintains data dependencies such as assumption, label, environment and justification on a cluster of machines in parallel and efficiently updates changes in a large amount of inferred datasets. We deployed the proposed ATMS on a cluster with 5 machines, conducted OWL/RDFS reasoning over University benchmark data (LUBM) and evaluated our system in terms of its performance and functionalities such as assertion, explanation and retraction. In our experiments, the proposed system performed the operations in a reasonably short period of time for over 80GB inferred LUBM2000 dataset.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.10
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• pp.520-529
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• 2005

A feature-based 3D modeling algorithm is presented in this paper. Since conventional methods use depth-based techniques, they need much time for the image matching to extract depth information. Even feature-based methods have less computation load than that of depth-based ones, the calculation of modeling error about whole pixels within a triangle is needed in feature-based algorithms. It also increase the computation time. Therefore, the proposed algorithm consists of three phases, which are an initial 3D model generation, model evaluation, and model refinement phases, in order to acquire an efficient 3D model. Intensity gradients and incremental Delaunay triangulation are used in the Initial model generation. In this phase, a morphological edge operator is adopted for a fast edge filtering, and the incremental Delaunay triangulation is modified to decrease the computation time by avoiding the calculation errors of whole pixels and selecting a vertex at the near of the centroid within the previous triangle. After the model generation, sparse vertices are matched, then the faces are evaluated with the size, approximation error, and disparity fluctuation of the face in evaluation stage. Thereafter, the faces which have a large error are selectively refined into smaller faces. Experimental results showed that the proposed algorithm could acquire an adaptive model with less modeling errors for both smooth and abrupt areas and could remarkably reduce the model acquisition time.

• Journal of Broadcast Engineering
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• v.20 no.4
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• pp.509-520
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• 2015

A design for the merge mode of three dimensional High Efficiency Video Coding (3D-HEVC) is proposed in this paper. The proposed design can reduce the implementation complexity by removing the duplicated modules of the HEVC. For the extension codec, the implementation complexity is as crucial as coding efficiency, meaning if possible, extension codec needs to be easily implemented through by reusing the design of the legacy codec as-is. However, the existing merging process of 3D-HEVC had been built-in integrated in the inside of the HEVC merging process. Thus the duplicated merging process of HEVC had to be fully re-implemented in the 3D-HEVC. Consequently the implementation complexity of the extension codec was very high. The proposed 3D-HEVC merge mode is divided into following two stages; the process to reuse the HEVC modules without any modification; and the reprocessing process for newly added and modified merging modules in 3D-HEVC. By applying the proposed method, the re-implemented HEVC modules, which accounted for 51.4% of 3D-HEVC merge mode confirmed through the operational analysis of algorithm, can be eliminated, while maintaining the same coding efficiency and computational complexity.

• Smart Media Journal
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• v.7 no.1
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• pp.37-44
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• 2018

Utilizing sequence control and numerical computing, embedded devices are used in a variety of automated systems, including those at industrial sites, in accordance with their control program. Since embedded devices are used as a control system in corporate industrial complexes, nuclear power plants and public transport infrastructure nowadays, deliberate attacks on them can cause significant economic and social damages. Most attacks aimed at embedded devices are data-coded, code-modulated, and control-programmed. The control programs for industry-automated embedded devices are designed to represent circuit structures, unlike common programming languages, and most industrial automation control programs are designed with a graphical language, LAD, which is difficult to process static analysis. Because of these characteristics, the vulnerability analysis and security related studies for industry automation control programs have only progressed up to the formal verification, real-time monitoring levels. Furthermore, the static analysis of industrial automation control programs, which can detect vulnerabilities in advance and prepare for attacks, stays poorly researched. Therefore, this study suggests a method to present a discussion on an industry automation control program designed to represent the circuit structure to increase the efficiency of static analysis of embedded industrial automation programs. It also proposes a medium term translation technology exploiting LLVM IR to comprehensively analyze the industrial automation control programs of various manufacturers. By using LLVM IR, it is possible to perform integrated analysis on dynamic analysis. In this study, a prototype program that converts to a logical expression type of medium language was developed with regards to the S company's control program in order to verify our method.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.150-159
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• 2014

The latest video coding standard, HEVC can improve the coding efficiency significantly compared with the H.264/AVC. However the HEVC encoder requires much larger computational complexities. The longer 8-tap interpolation filter of the HEVC which is used in a non-integer motion estimation is one of the reasons and this paper aims to reduce the computational complexities. First of all, three shorter-tap interpolation filters for a motion estimation process are tested rather than the use of a standard interpolation filter. In addition, the fast searching strategies to reduce the number of comparisons for choosing the best non-integer motion vector are proposed. Finally, the interpolation process is selectively applied according to the searching strategy. By combining all of the techniques, the experimental results show that the encoding times can be reduced by 13.6%, 18.5% and 21.1% with the coding efficiency penalties of 0.7%, 1.5% and 2.5%, respectively. For the full-HD video sequences, the coding efficiency penalties are reduced to 0.4%, 1.1% and 1.6% at the same level of the encoding time savings, which shows the effectiveness of the proposed schemes for the high resolution video sequences.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.