• Journal of Korea Multimedia Society
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• v.8 no.2
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• pp.249-257
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• 2005

This paper aims at reducing aliasing in pixel-based rendering for 3D implicit surfaces by shifted multi Z-buffers. The voxelized implicit surfaces with high resolution take so much time in generating high Quality image without aliasing. So in rendering a voxelized implicit surfaces, a new antialiasing method which can generate a high quality image at a lower resolution is required. Therefore, this paper suggests that a method which get various sampling values by shifting several z-buffers in each voxel and average them, The advantages are effective memory, simple calculation and easy convergence with various filters. But, the increase of number of z-buffer also increase the consuming time rapidly. Therefore, the research for representing the relation the degree of image quality with the consumption of time as a number is required.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.1
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• pp.76-80
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• 2010

It is floating to security of information and the early assignment that it is important it processes and to transmit in inundations of information that I changed suddenly. I used the encryption/decryption process that applied simple substitution and mathematical calculation algorithm at theory and encryption transmission steps protective early information. Hardware and financial loss are using spurious random number to be satisfied with the random number anger that isn't real random number to size so much perfect information protection using One-time pad for applying this. I was transformed into serial test under a test to prove spurious random number anger, and it is into random number anger stronger, and the transformation serial test that proposes is proving it in algorithm speed and efficiency planes.

• The Journal of the Acoustical Society of Korea
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• v.32 no.6
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• pp.541-547
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• 2013

The speech quality of multi-party audio telephony between two, three or more participants is decreased by audio volume imbalance, audio volume saturation and noise level increase. To solve this issue, this paper proposes an advanced audio mixing algorithm for software-based multi-point control unit. Our approach is based on the combined voice activity detection and gain control technique that consists of a set of algorithms that classify audio signals, estimate audio volumes, adjust gain factors and mix audio signals of all channels. The proposed audio mixing algorithm is computationally efficient, delivers high-quality speech, and is suitable for use in any practical multi-party audio telephony.

• Journal of Korea Multimedia Society
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• v.5 no.2
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• pp.231-238
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• 2002

As electronic commerce is becoming more popular on the Internet, smart cards have been used for safe transfers and transactions on I-commerce popularly. Especially, Java Card considered as a COS for the next generation must take advantage of the good points of Java Language by using this language and making programs asked for by various demands. In this paper, we proposed efficient management system of mileage on the Internet using Java Card. The system has security for data and the simplicity of application development by Java Card cryptography. The system is an independent program saved un Java Card and can calculate and save mileage, although the characteristic of the mileage is different from others through the calculating Process of the Card. Also, the system is developed to encourage the efficiency of a system after comparing and contrasting between established systems and the newly designed one in simulation.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.977-983
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• 2009

Recently, several DDP, DDO and COS-based block ciphers have been proposed for hardware implementations with low cost. However, most of them are vulnerable to related-keyt attacks. A 12-round block cipher SCOS-3 is desinged to eliminate the weakness of DDP, DDO and COS-based block ciphers. In this paper, we propose a related-key differential attack on an 11-round reduced SCOS-3. The attack on an 11-round reduced SCOS-3 requires $2^{58}$ related-key chosen plaintexts and $2^{117.54}$ 11-round reduced SCOS-3 encryptions. This work is the first known attack on SCOS-3. Therefore, SCOS-3 is still vulnerable to related-key attacks.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.411-414
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• 2008

In this paper, we present a determination method of quantization skipping condition for H.264/AVC video encoding standard. In order to reduce the complexity of quantization process that is coming from Integer discrete cosine transform, a quantization skipping condition is derived by the analysis of integer transform and quantization processes. The experimental results show that the proposed algorithm has the capability to reduce the computational complexity of CPU operation time about 10-25(%)

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.158-163
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• 2001

Current Source Inverter(CSI), operated in square wave mode, is more efficient thant the PWM CSI because of increased cost, greater complexity of control algorithm and substantial switching losses, EMI. But, the square wave output current of CSI, rich in low order harmonics produce motor torque ripples. Therefore, in this paper, describes active power filters for compensating square wave input current of current source induction motor. Also, notch filtering as compensation algorithm is employed. To confirm the validity of proposed system, PSIM simulation results are presented and discussed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.131-134
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• 2007

In this paper, we propose the 1D-CZP pattern for FPGA verification. The algorithm that was implemented by Verilog-HDL on FPGA board is verified before the chip is producted. Input through the external sensor might not be enough to verify the algorithm on FPGA board. Hence, both external input and internal input can lead the verification of the algorithm. This paper suggests the hardware implementation of compact 1D-CZP pattern that has the random input. It is useful to analyze the characteristics of the filter frequencies and organized as ROM Table which is efficient to Modulus operation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.454-460
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• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.