• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11B
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• pp.1169-1177
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• 2009

This paper presents an energy efficient MAC protocol for delay-sensitive data transmission over wireless sensor network. In general, energy consumption and delay depend on Channel Monitoring Interval and data sensing period at each sensor node. Based on this fact, we propose a new preamble structure to effectively advertise Channel Monitoring Interval and avoid the overhearing problem. In order to pursue an effective tradeoff between energy consumption and delay, we also develop a Channel Monitoring Interval determining algorithm that searches for a sub-optimal solution with a low computational complexity. Finally, experimental results are provided to compare the proposed MAC protocol with existing sensor MAC protocols.

• The Journal of the Acoustical Society of Korea
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• v.25 no.1
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• pp.14-20
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• 2006

In this paper. a novel technique to set up the initial weights in BSS of delayed mixtures is proposed. After analyzing Eigendecomposition for the correlation matrix of mixing data. the initial weights are set from the Eigenvectors ith delay information. The Proposed setting of initial weighting method for conventional FDICA technique improved the separation Performance. The computer simulation shows that the Proposed method achieves the improved SIR and faster convergence speed of learning curve.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.183-195
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• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4997-5006
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• 2010

A flash-memory-based SSDs(Solid State Disks) are one of the best media to support portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major database storage components for desktop and server computers. However, we need to improve traditional storage management schemes based on HDD(Hard Disk Drive) and RAID(Redundant array of independent disks) due to the relatively slow or freezing characteristics of write operations of SSDs, as compared to fast read operations. In order to achieve this goal, we propose a new storage management scheme called Hetero-Mirroring based on traditional HDD mirroring scheme. Hetero-Mirroring-based scheme improves RAID-1 operation performance by balancing write-workloads and delaying write operations to avoid SSD freezing. Our test results show that our scheme significantly reduces the write operation overheads and freezing overheads, and improves the performance of traditional SSD-RAID-1 scheme by 18 percent, and the response time of the scheme by 38 percent.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5C
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• pp.534-539
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• 2006

In this paper, we propose a new frame prediction filtering technique and a hardware(H/W) architecture for scalable video coding. We try to evaluate MCTF(motion compensated temporal filtering) and hierarchical B-picture which are a technique for eliminate correlation between video frames. Since the techniques correspond to non-causal system in time, these have fundamental defects which are long latency time and large size of frame buffer. We propose a new architecture to be efficiently implemented by reconfiguring non-causal system to causal system. We use the property of a repetitive arithmetic and propose a new frame prediction filtering cell(FPFC). By expanding FPFC we reconfigure the whole arithmetic architecture. After the operational sequence of arithmetic is analyzed in detail and the causality is imposed to implement in hardware, the unit cell is optimized. A new FPFC kernel was organized as simple as possible by repeatedly arranging the unit cells and a FPFC processor is realized for scalable video coding.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1904-1913
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• 2021

With the proliferation of smart phones and the development of IoT technology, it has become possible to collect personal data for public purposes. However, users are afraid of voluntarily providing their private data due to privacy issues. To remedy this problem, mainly three techniques have been studied: data disturbance, traditional encryption, and homomorphic encryption. In this work, we perform simulations to compare them in terms of accuracy, message length, and computation delay. Experiment results show that the data disturbance method is fast and inaccurate while the traditional encryption method is accurate and slow. Similar to traditional encryption algorithms, the homomorphic encryption algorithm is relatively effective in privacy preserving because it allows computing encrypted data without decryption, but it requires high computation costs as well. However, its main cost, arithmetic operations, can be processed in parallel. Also, data analysis using the homomorphic encryption needs to do decryption only once at any number of data.

• Journal of the Korea Society of Computer and Information
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• v.29 no.6
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• pp.1-12
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• 2024

Deep learning with faster and more accurate results requires large amounts of storage space and large computations. Accordingly, many studies are using hardware accelerators for quick and accurate calculations. However, the performance bottleneck is due to data movement between the hardware accelerators and the CPU. In this paper, we propose a data prefetch strategy that can efficiently reduce such operational bottlenecks. The core idea of the data prefetch strategy is to predict the data needed for the next task and upload it to local memory while the hardware accelerator (Matrix Multiplication Unit, MMU) performs a task. This strategy can be enhanced by using a dual buffer to perform read and write operations simultaneously. This reduces latency and execution time of data transfer. Through simulations, we demonstrate a 24% improvement in the performance of hardware accelerators by maximizing parallel processing with dual buffers and bottlenecks between memories with data prefetch.