• Journal of Korea Spatial Information System Society
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• v.7 no.3 s.15
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• pp.55-65
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• 2005

This paper presents a bulk insertion technique for efficiently inserting data items. Traditional moving object database focused on efficient query processing that happens mainly after index building. Traditional index structures rarely considered disk I/O overhead for index rebuilding by inserting data items. This paper, to solve this problem, describes a new bulk insertion technique which efficiently induces the current positions of moving objects and reduces update cost greatly. This technique uses buffering technique for bulk insertion in spatial index structures such as R-tree. To analyze split or merge node, we add a secondary index for information management on leaf node of primary index. And operations are classified to reduce unnecessary insertion and deletion. This technique decides processing order of moving objects, which minimize split and merge cost as a result of update operations. Experimental results show that this technique reduces insertion cost as compared with existing insertion techniques.

• The Journal of the Korea Contents Association
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• v.10 no.1
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• pp.68-77
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• 2010

In this paper, we propose a new log buffer management scheme considering the accessibility of the data. Our proposed scheme evaluates the worth of the merge of log blocks. It conducts the merge operations between infrequently updated data and the data blocks and postpones as much as possible the merge operations between frequently updated data and the data blocks. As a result, the proposed method prevents the unnecessary merge operations, reduces the number of the erase operations, and improves the utilization of the flash memory storage. In order to show the superiority of the proposed scheme, we compare it with BAST and FAST. It is shown through performance evaluation that the proposed method achieves about 25% and 65% performance improvements over BAST and FAST on average in terms of the number of the erase operations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.407-413
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• 2015

In this paper, a DFPA(decimal floating-point adder) designed a pipeline structure that uses a LZA(leading zero anticipator) to reduce critical route to shorten delay to improve the speed of operation processing. The evaluation and verification of performance of proposed DFPA applied the Flowrian tool with simulation and Cyclone III FPGA was set as the target on the Quartus II tool for the synthesis. The proposed method compared and verified to proposed the other method using same input data. As a result, the performance of proposed method is improved 11.2% and 5.9% more than L.K.Wang's method and etc.. Also, it is confirmed that improvement of operation processing speed and reduction of the number of delay elements on critical path.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.366-370
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• 2008

NAND 플래시 메모리는 특성상 쓰기 횟수가 제한적이라는 단점을 가지고 있어 쓰기 연산이 빈번히 발생하게 되면 NAND 플래시 메모리의 수명이 줄어든다. 이러한 문제점을 해결하기 위해 NAND 플래시 메모리의 특성을 고려한 지연 쓰기 기법이 연구되고 있다. 하지만 지연 쓰기를 하기 때문에 쓰기 횟수는 줄어들지만 캐시 적중률이 낮아진다. 이러한 문제해결을 위해 본 논문에서는 NAND 플래시 메모리 기반 파일 시스템을 위한 더블 캐시 정책을 제안한다. 더블 캐시는 실질적인 캐시인 Real Cache와 요구 페이지의 패턴을 관찰하기 위한 Ghost Cache로 구성된다. 이 정책은 Real Cache에서의 지연 쓰기를 하지 않고, Ghost Cache 공간에서 dirty페이지와 clean페이지를 활용하여 효율적인 지연 쓰기가 가능하도록 설계함으로써 쓰기 횟수를 줄이고, 적중률을 높인다.

• Journal of KSNVE
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• v.5 no.4
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• pp.453-460
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• 1995

본 논문에서는 정현파 소음을 제어하기 위한 filtered-x LMS에 바탕을 둔 새로운 적응 알고리듬을 제안하였다. 이러한 알고리듬은 두개의 연속적인 계수조정 식으로, 제어기의 계수를 조정한다. 서로 독립인 각 주파수별로 처리하기 때문에 빠른 수렴을 얻을 수 있다. 두번째식은 이차경로로 인한 위상지연을 추정한다. 정현 파 신호 주파수보다 4배 이상 빠른 표본화 주파수를 선택하여 추정된 위상지연 추정 값은 $2{\pi}f_0$만큼 오차를 나타내며, 이 값은 $\pi$2보다 작다. 정현파 신호의 주파수를 알면 이러한 오차는 $2{\pi}f_0$를 더함으로써 제거할 수 있다. 이러한 방법은 위상지연이 $\pi$2보다 큰 경우 수렴속도를 증가시킨다는 사실을 실험을 통하 여 알 수 있다. 추정된 위상지연은 제어기 계수값을 조정하는데 필요한 필터링된 참조신호를 발생시키믄데 사용된다. 참조신호의 위상지연이 각 주파수 성분별로 수행 되기 때문에, 콘볼루션 연산이 생략되어 계산량을 줄일 수 있다. 또한 연속적으로 위상지연을 추정하기 때문에 시변 상황에 적용이 가능하다. 조정식의 수렴조건을 유도하였다. 제안된 알고리듬은 제어기 계수를 추정하는데 바이어스가 없으며, 위상 지연추정을 위한 수렴상수의 최대허용치는 제어기계수에 대한 수렴상수에 반비례함을 이론적으로 분석을 통해 알 수 있다. 모의실험을 통하여 제안된 알고리듬이 filtered-x LMS 알고리듬에 바탕을 둔 다른 알고리듬보다 환경변화에 우수한 성능을 보임을 알 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1188-1195
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• 2006

This paper presents an efficient design method of 2-D state-space digital filter based on an improved branch-and -bound algorithm. The resultant 2-D state-space digital filters whose coefficients are represented as the sum of two power-of-two terms, are attractive for high-speed operation and simple implementation. The feasibility of the proposed method is demonstrated by several experiments. The results show that the approximation error and group delay characteristic of the resultant filters are similar to those of the digital filters which designed in the continuous coefficient space.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.141-149
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• 2006

In this paper, we introduce an improved algorithm for computing matrix triple product that commonly arises in primal-dual optimization method. In computing $P=AHA^{t}$, we devise a single pass algorithm that exploits the block diagonal structure of the matrix H. This one-phase scheme requires fewer floating point operations and roughly half the memory of the generic two-phase algorithm, where the product is computed in two steps, computing first $Q=HA^{t}$ and then P=AQ. The one-phase scheme achieved speed-up of 2.04 on Intel Itanium II platform over the two-phase scheme. Based on memory latency and modeled cache miss rates, the performance improvement was evaluated through performance modeling. Our research has impact on performance tuning study of complex sparse matrix operations, while most of the previous work focused on performance tuning of basic operations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.185-191
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• 2018

This study examined the type and extent of interruption between induced emotion and succeeding arithmetic operation. The experiment was carried out to determine the influence of the induced emotions (anger, joy, and sorrow) and stimulus types (picture and sentence) on the cognitive process load that may block the interactions among the constituents of working memory. The study subjects were 32 undergraduates who were similar with respect to age and education parameters and were especially instructed to attend to induced emotion by imitation of facial expression and to make a correct decision during the remainder calculation task. In the results, the stimulus types did not exhibit any difference but there was a significant difference among the induced emotion types. The difference was observed in slower response time at positive emotion(joy condition) as compared with other emotions(anger and sorrow). More specifically, error and delayed correct response rate for emotion types were analysed to determine which phase the slower response was associated with. Delayed responses of the joy condition by sentence-inducing stimulus were identified with the error rate difference, and those by picture-inducing stimulus with the delayed correct response rate. These findings not only suggest that induced positive emotion increased response time compared to negative emotions, but also imply that picture-inducing stimulus easily affords arithmetic fluctuation whereas sentence-inducing stimulus results in arithmetic failure.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.87-94
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• 2003

As the number of the Internet users increases explosively, a solution for this problem is web caching. So, many techniques on improving cache server performance have been suggested. In this paper, we analyze the cause of the bottleneck in cache servers, and propose an arbitral thread and delayed caching mechanism as a solution. We use an arbitral thread in order to provide a quick service to user requests through eliminating the ready multi-thread search problem in case of disk writing operation. We also use delayed caching in order to provide stable system operation through avoiding overloaded disk operation and queue threshold. Proposed cache server is implemented through modification on SQUlD cache server, and we compare its performance with the original SQUID cache server.