• Journal of Korea Multimedia Society
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• v.3 no.4
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• pp.347-355
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• 2000

This paper presents an adaptive AEC(acoustic echo canceller) based on the wavelet transform using M-channel subband QMF filter banks. The proposed algorithm improves the performance of AEC with a realtime process by a low complexity of wavelet transform filter banks, a subband processing and a orthogonality of wavelet subband filter. Adaptive filter coefficients of each subband are updated using LMS algorithm with a low complexity and a easy realization for a realtime processing and a reduction of hardware cost. For a input signal, a white Gaussian noise and a real speech signal with a environment noises are used for a performance estimation of the proposed algorithm. As a result of computer simulation, the proposed AEC has a low asymptotic error, a low computation complexity and a robust performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.785-793
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• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.9-15
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• 2006

In this paper, signal processing techniques for noncoherent impulse-radio-based UWB (IR-UWB) communication system are proposed to provide system implementation of low power consumption and low complexity. The proposed system adopts a simple modulation technique of OOK (on-oft-keying) and noncoherent signal detection based on signal amplitude. In particular, a technique of a novel high speed digital sampler using a stable, lower reference clock is developed to detect nano-second pulses and recover digital signals from the pulses. Also, a 32 bits Turyn code for data frame synchronization and a convolution code as FEC are applied, respectively. To verify the proposed signal processing techniques for low power, low complexity noncoherent IR-UWB system, the proposed signal processing technique is implemented in FPGA and then a short-range communication system for wireless transmission of high quality MP3 data is designed and tested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1677-1690
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• 1997

Block-transform coding is one of the most popular approaches for image compression. For example, DCT is widely used in the internaltional standards standards such as MPEG-1, MPEG-2, JPEG, and H.261. In the block-based transform coding, blocking artifacts may appear along block boundaries, and they can cause severe image degradation eqpecially when the transform coefficients are coarsely quantized. In this paper, we propose a new method for blocking artifacts reduction in transform-coded images. For blocking artifacts reduction, we add a correction term, on a block basis, composed of a linear combination of 28 basis images that are orthonormal on block boundaries. We select 28 DCT kernel functions of which boundary values are linearly independent, and Gram-Schmidt process is applied to the boundary values in order to obtain 28 boundary-orthonormal basis images. A threshold of bolock discontinuity is introduced for improvement of visual quality by reducing image blurring. We also investigate the number of basis images needed for efficient blocking artifacts reduction when the compression ratio changes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.27 no.1
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• pp.54-61
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• 2023

With the development of IoT technologies and artificial intelligent, diverse digital image equipments are being used in industrial sites. Because image data can be easily damaged by noise while it's obtained with a camera or a sensor and the damaged image has a bad effect on the process of image processing, noise removal is being demanded as preprocessing. In this thesis, for the restoration of image damaged by the noise of random impulse, a switching filter algorithm based on noise estimation was suggested. With the proposed algorithm, noise estimation and error distraction were carried out according to the similarity of the pixel values in the local mask of the image, and a filter was chosen and switched depending on the ratio of noise existing in the local mask. Simulations were conducted to analyze the noise removal performance of the proposed algorithm, and as a result of magnified image and PSNR comparison, it showed superior performance compared to the existing method.

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.01a
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• pp.39-42
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• 2023

최근 온라인 게임 산업이 급속도로 확장됨과 더불어 Gamebot과 같은 비정상적인 프로그램으로 인한 게임 서비스 피해사례가 급격하게 증가하고 있다. 특히, 대표적인 게임 장르 중 하나인 FPS(First-Person Shooter)에서 Aimbot의 사용은 정상적인 이용자들에게 재미 요소를 잃어버리게 하고 상대적 박탈감을 일으켜 게임의 수명을 줄이는 원인이 된다. 비정상 게임 이용자의 근절을 위해서 메모리 변조 및 불법 변조 프로그램 접근 차단 기법과 불법 프로그램 사용의 패턴 모니터링과 같은 기법들이 제안되었지만, 우회 프로그램 및 새로운 패턴을 이용한 비정상적인 프로그램의 개발에는 취약하다는 단점이 있다. 따라서, 본 논문에서는 정상적인 게임 이용자의 패턴만 학습함으로써 비정상 이용자 검출을 가능하게 하는 딥러닝 기반 단일 클래스 분류 기법을 제안하며, 가장 빈번하게 발생하는 치트(Cheat) 유형인 FPS 게임 내 Aimbot 사용 감지에 초점을 두었다. 제안된 비정상 게임 이용자 감지 시스템은 정상적인 사용자의 마우스 좌표를 데카르트 좌표계(Cartesian coordinates)와 극좌표계(Polar coordinates)의 형태로 패턴을 추출하는 과정과 정상적인 마우스 동작 기록으로 부터 학습된 LSTM 기반 Autoencoder의 복원 에러에 따른 검출 과정으로 구성된다. 실험에서 제안된 모델은 FPS 게임 내 마우스 동작을 기록한 공개 데이터셋인 CSGO 게임 데이터셋으로 부터 학습되었으며, 학습된 모델의 테스트 결과는 데카르트 좌표계로부터 훈련된 제안 모델이 비정상 게임 이용자를 분류하는데 적합함을 입증하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.79-89
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• 2011

Recent development of embedded processors makes it possible to play back video contents in real-time on portable devices. Because of their limited battery capacity and low computational performance, however, portable devices still have significant problems in real-time decoding of high quality or high resolution compressed video. Although previous approaches are successful in achieving complexity-scalable decoder by controlling computational complexity of decoding elements, they cause significant objective quality loss coming from mismatch between encoder and decoder. In this paper, we propose a selective B slice skip-decoding method to implement a low complexity video decoder. The proposed method performs selective skip decoding process of B slice which satisfies the proposed conditions. The skipped slices are reconstructed by simple reconstruction method utilizing adjacent reconstructed pictures. Experimental result shows that proposed method not only reduces computational complexity but also maintains subjective visual quality.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.46-54
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• 2011

In this paper, we propose a low-complexity loop filtering method depending on transform-block regions. Block adaptive loop filter (BALF) was developed to improve about 10% in compression performance for the next generation video coding. The BALF employs the Wiener filter that makes reconstructed frames close to the original ones and transmits filter-related information. However, the BALF requires high computational complexity, while it can achieve high compression performance because the block adaptive loop filter is applied to all the pixels in blocks. The proposed method is a new loop filter that classifies pixels in a block into inner and boundary regions based on the characteristics of the integer transform and derives optimum filters for each region. Then, it applies the selected filters for the inner and/or boundary regions. The decoder complexity can be adjusted by selecting region-dependent filter to be used in the decoder side. We found that the proposed algorithm can reduce 35.5% of computational complexity with 2.56% of compression loss, in case that only boundary filter is used.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.58-66
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• 2009

Recently the emerging demands of the light-video encoder promotes lots of research efforts on DVC (Distributed Video Coding). As an appropriate video compression method, DVC has been studied, and Wyner-Ziv (WZ) video compression is its one representative structure. The WZ encoder splits the image into two kinds of frames, one is key frame which is compressed by conventional intra coding, and the other is WZ frame which is encoded by WZ coding. The WZ decoder decodes the key frame first, and estimates the WZ frame using temporal correlation between key frames. Estimated WZ frame (Side Information) cannot be the same as the original WZ frame due to the absence of the WZ frame information at decoder. As a result, the difference between the estimated and original WZ frames are regarded as virtual channel noise. The WZ frame is reconstructed by removing noise in side information. Therefore precise noise estimation produces good performance gain in WZ video compression by improving error correcting capability by channel code. But noise cannot be estimated precisely at WZ decoder unless there is good WZ frame information, and generally it is estimated from the difference of corresponding key frames. Also the estimated noise is limited by comparing with frame level noise to reduce the uncertainty of the estimation method. However these methods cannot provide good noise estimation for every frame or each bit plane. In this paper, we propose a noise nodel selection method which chooses a better noise model for each bit plane after generating candidate noise models. Experimental result shows PSNR gain up to 0.8 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.