• Review of KIISC
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• v.30 no.5
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• pp.111-119
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• 2020

동형암호(homomorphic encryption)는 암호화된 데이터 사이에서 임의의 연산을 가능하게 하는 유망한 암호학적 스킴(scheme)이다. 이를 활용하면 암호화된 데이터를 복호화하지 않고, 암호화된 상태에서 임의의 연산을 수행 할 수 있을 뿐만아니라, 격자를 기반(lattice-based)으로 하여 양자 알고리즘에 내성(resistant)이 있어 안전하다. 하지만, 동형암호를 이해하기 위해서는 전문적인 암호 또는 계산적인 이론의 지식과 이해가 필요하다. 따라서 본 논문에서는 완전동형암호(fully homomorphic encryption)의 기저에 있는 LWE(learning with error) 문제에서부터 완전동형암호의 핵심인 NAND 게이트와 부트스트래핑(bootstrapping)까지의 과정을 어렵지 않게 설명하여 초보자들의 이해를 돕고자 한다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.691-694
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• 2003

Density gradient method is used to analyze the quantum effect in MOSFET, Quantization effect in the poly gate leads to a negative threshold voltage shift, which is opposed to the positive shift caused by quantization effect in the channel. Quantization effects in the poly gate are investigated using the density gradient method, and the impact on the short channel effect of double gate device is more significant.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.16-21
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• 1994

A 3-terminal pin-type photosensor with gate contrail is fabricated using standard silicon CMOS IC process. The photosensor of a $100{\mu}m{\times}120{\mu}m$ size has dark current less than 1nA and its breakdown voltage is -14V with a depletion capacitance 0.75 pF at -5V reverse bias. Responsivity at 0V gate voltage is 0.25A/W at $0.633{\mu}m$ wavelength, 0.19A/W at $0.805{\mu}m$. Responsivity increases with increasing gate voltage. The integrated circuit of photosensor and CMOS inverter shows $22K{\Omega}$ transimpedance and photocurrent of $90{\mu}A$ switchs the output state of digital inverter without additional amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.495-508
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• 2023

This paper proposes a method to find out the type and location information of Pauli X, Y, Z errors generated in quantum channels using only the quantum information processing part of the multiple-rate quantum turbo short-block code without external help from the classical information processing part. In order to obtain the location information of the Pauli X,Y error, n-auxiliary qubits and n-CNOT gates were inserted into the C[n,k,2] QSBC-QURC encoder. As a result, the maximum coding rate is limited to about 1/2 as the trade-off characteristics. The location information of the Pauli Z error for C[n,k,2] QSBC-QURC was obtained through the Clifford-based stabilizer measurement. The proposed method inherits all other characteristics of C[n,k,2] QSBC-QURC except for the coding rate.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.603-608
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• 2016

Encoding means converting or processing form or format of information into the other forms to standardize, secure, improve processing speed, store saving spaces and etc. Also, Encoding is converting the information so as to do transmit other form on the sender's information to the receiver in Information-Communication. The device that is conducting the processing is called the encoder. In this dissertation, proposes an encoder of the most basic 4-to-2 encoder. proposed encoder consists of two OR-gate and the proposed structure designs and optimize the spacing of the cell for the purpose of minimizing noise between wiring. Through QCADesigner conducts simulation of the proposed encoder and analyzes the results confirm the effectiveness.

• Proceedings of the Korea Contents Association Conference
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• 2007.11a
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• pp.837-841
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• 2007

최근 영상을 중심으로 여러 형태의 정보를 결합하여 저장하거나 전송하는 멀티미디어가 많은 관심을 받고 있다. 현재 카메라와 관련된 동영상 캡처기술은 Motion JPEG이 주류를 이루고 있으며, 텔레비전, DMB 등의 방송 분야 및 DVD, VCR 분야에서는 MPEG-2, MPEG-4, H.264 및 WMV9 등의 압축 코덱이 채용되고 사용되고 있다. 그러나 이러한 다양한 영상 표준방식은 디코딩시 호환성 문제가 발생하게 되고 이에 따라 통합 코덱 연구가 필요하다. 이에 본 논문은 일반적 스텝 양자화외에 데드존 양자화를 사용하고 "$4{\times}4$", "$4{\times}8$", "$8{\times}4$", "$8{\times}8$"의 다양한 블록크기의 변환을 지원하는 VC-1을 기반으로 한 ITIQ C언어를 통해 시뮬레이션하고 최적화된 결과를 VHDL로 구현하여 향후 통합코덱 연구에 응용 가능하도록 연구 및 분석평가 하였다. 설계결과 4:2:0의 YCbCr포맷의 최초 $16{\times}16$블록을 복원하는데 483~510클록이 소요되었고 Xilinx XCVPC100 FF1696-6 환경에서 93,128개의 게이트 수와 71.469MHz의 동작속도를 나타내었다. 이는 640*480 크기의 컬러영상을 디코딩 하는데 프레임 당 최대 0.0074초가 소요됨을 의미하며 초당 30프레임의 영상에서도 0.222초면 디코딩이 가능한 결과이다.

• Journal of IKEEE
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• v.23 no.3
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• pp.811-816
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• 2019

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD) was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-O superlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). This thick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that it should be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of future silicon-based three-dimensional integrated circuit(3DIC).

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.279-279
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• 2011

나노 입자를 이용한 비휘발성 메모리 소자의 전기적 특성 향상을 위하여 일함수가 Si 보다 큰 금속, 금속산화물, 금속 실리사이드 나노입자를 이용한 다양한 형태의 메모리 구조가 제안되어져 왔다.[1] 특히 이와 같은 나노 부유 게이트 구조에서 터널 절연막의 구조를 소자의 동작 속도를 결정하는데 이는 터널링 되어 주입되는 전자의 확률에 의존하기 때문이다. 양자 우물에 국한된 전하가 누설되지 않으면서 주입되는 전자의 터널링 확률을 증가시키기 위하여, dielectric constant 와 barrier height를 고려한 다양한 구조의 터널 절연막의 형태가 제안 되었다.[2-3] 특히 낮은 전계에서도 높은 터널링 확률은 메모리 소자의 동작 속도를 향상시킬 수 있다. 본 연구에서는 n형 Si 기판위에 Si3N4 및 HfAlO를 각각 1.5 nm 및 3 nm 로 atomic layer deposition 방법으로 증착하였으며 3~5 nm 지름을 가지는 $TiSi_2$ 및 $WSi_2$ 나노 입자를 형성한 후 컨트롤 절연막인 $SiO_2$를 ultra-high vacuum sputtering을 사용하여 20 nm 두께로 형성 하였다. 마지막으로 $200{\mu}m$ 지름을 가지는 Al 전극을 200 nm 두께로 형성하여 나노 부유 게이트 커패시터를 제작하였다. 제작된 소자는 Agilent E4980A precision LCR meter 및 HP 4156A precision semiconductor parameter analyzer 를 사용하여 전기용량-전압 및 전류-전압 특성분석을 하여 전하저장 특성 및 제작된 소자의 터널링 특성을 확인 하여 본 연구를 통하여 제작된 나노 부유 게이트 커패시터 구조가 메모리 소자응용이 가능함을 확인하였다.