• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.3
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• pp.497-502
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• 2018

An analog to digital converter(: ADC) has been designed to extract video signals of marine X-band radar and convert to digital signals in order to produce rainfall information. X-band weather radars are suitable for high temporal-spatial resolution observations of rainfall over local ranges but they are very expensive and require professional management. The marine radars with 10-2 cost facilitate data collection and management as well as economic benefits. To validate the usefulness of the developed ADC, comparative observations were made with weather radar for short term precipitation cases. The rainfall distribution of marine radar observations are consistent with that of weather radar within a radius of 15 km. This demonstrates the usability of marine radar for rainfall observations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.16-23
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• 2006

This paper presents the development of the fast Direction Finder using direct conversion method, which can intercept for short pulse signal of less' than 1 msec. in RF Down Converter, and CVDF(Correlative Vector Direction Finding) algorithm, which estimates DoA (Direction of Arrival). The configuration and characteristics of direction finder using 5-channel equi-spaced circular array antenna are presented and the direct conversion techniques for removing tuning time using I/Q demodulator are described. The CRLB of our model is derived, the principles of 2 kind of CVDF algorithm are explained and their characteristics are compared with CRLB w.r.t the number of samples and spacing ratio. The RF Down Converter prototype using direct conversion method is manufactured, the 2 kind of CVDF algorithm are applied and their performance are analyzed. Finally it is confirmed the LSE based CVDF algorithm is better than correlation-coefficient based except for ambiguity protection capabilities.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.2
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• pp.235-244
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• 2014

This paper describes the subarray channel configuration and calibration method for airborne AESA radar antenna. AESA radar demonstrator was designed and implemented for the digital beam-forming performance test of the 12 channel subarray structure. Magnitude and phase difference can be exist between the manufactured subarray channel. In this paper, calibration method for the subarray difference error was suggested. We measured digital monopulse slope in the subarray channel and verified the channel calibration effect. To verify the subarray channel operation, digital monopulse channel was compared with analog monopulse channel performance. AESA radar demonstrator was tested in the ground far field test range. Emulated single target was generated to test the detection and tracking performance of the demonstrator with the same waveform and search pattern. We verified that the detection and tracking performance of the 12 subarray digital monopulse channel was similar with the conventional analog monopulse channel. Also, ABF(Adaptive Beam-Forming) function for the sidelobe jammer was tested and effective operation was verified.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.921-926
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• 2015

For the over-heat protection purpose in power strip devices, over-current detection/protection circuits, such as bimetal, switching circuit, and microprocessor-based relay circuit, have been widely setup in high-end products. Most of these circuits are connected to the power line in parallel and, thus, they are sensitive to the line voltage and current distortion. Moreover, these protection circuits are often costly and, therefore, it is hard to meet the commercial requirements. A low-cost over-current detection circuit with the contactless current transducer is designed and tested in this paper. The detection circuit is galvanically isolated from the power line and, thus, less sensitive to the line voltage distortion. The experimental results show that the proposed circuit accurately operates despite of its simple structure and low-cost electronic parts.

• Journal of Bio-Environment Control
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• v.5 no.2
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• pp.111-119
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• 1996

The purpose of this study is to construct the main system of simulator for the environment control of agricultural production facilities. The model describing the system was based on the energy and mass balance in an unsteady - state situation. The model consist of the three major parts : the main model, the light model, and the environmental control model, and each part was separated to be developed individually. The main model which is the core of this system includes the thermal model, the soil model, the ventilation model, the cultivation model, and the carbon dioxide model. And also the environmental control model includes the thermal curtain model, the heater/cooler model and the underground heat exchanger model. The equations used in this model were written in analog programming methods using PCSMP The simulator was evaluated through comparison between simulated and measured temperatures controlled during daytime and night. The results showed good agreements between the predicted and measured temperatures.

• The Journal of the Acoustical Society of Korea
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• v.41 no.5
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• pp.507-517
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• 2022

The PhotoAcoustic Microscopy (PAM) has been proved to be a useful tool for biological and medical applications due to its high spatial and contrast resolution. PAM is based on transmission of laser pulses and reception of PA signals. Since the strength of PA signals is generally low, not only are high-performance optical and acoustic modules required, but high-performance electronics for imaging are also particularly needed for high-quality PAM imaging. Most PAM systems are implemented with a combination of several pieces of equipment commercially available to receive, amplify, enhance, and digitize PA signals. To this end, PAM systems are inevitably bulky and not optimal because general purpose equipment is used. This paper reports a PA signal receiving system recently developed to attain the capability of improved Signal to Noise Ratio (SNR) and Contrast to Noise Ratio (CNR) of PAM images; the main module of this system is a low noise, wideband signal receiver that consists of two low-noise amplifiers, two variable gain amplifiers, analog filters, an Analog to Digital Converter (ADC), and control logic. From phantom imaging experiments, it was found that the developed system can improve SNR by 6.7 dB and CNR by 3 dB, compared to a combination of several pieces of commercially available equipment.

• Journal of Advanced Navigation Technology
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• v.11 no.1
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• pp.9-16
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• 2007

In this paper, the Bit Error Ratio (BER) performances of the D8PSK modulation schemes for VDL Mode-2 are analyzed according to the matched and unmatched cases of the channel filters. The carrier frequency and phase offset effects are analyzed with unmatched case. Generally in digital transmission techniques, the Root Raised Cosine filters which are used as channel filters are applied to both sides at transmitter and receiver in order to achieve no ISI, but in VDL Mode-2, the Raised Cosine Filter is used only in transmission section and the receiver section uses general low pass filter, therefore we could not achieve ISI reduction effects but can have better spectrum quality. From the simulation results, the error probability is increased slightly (1~2dB) with use of un-matched channel filter, we got the conclusions that carrier phase offset do not effect to bit error ratio, but the frequency offset effect is so serious. Finally, narrow band D8PSK modulation signals are generated by the use of Digital Up-Converter and then its features are compared with analog modulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.