• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.6
• /
• pp.177-181
• /
• 2016

This paper analyzes the host cache effectiveness in full virtualization, particularly associated with journaling of guests. We observe that the journal access of guests degrades cache performance significantly due to the write-once access pattern and the frequent sync operations. To remedy this problem, we design and implement a novel caching policy, called PDC (Pollution Defensive Caching), that detects the journal accesses and prevents them from entering the host cache. The proposed PDC is implemented in QEMU-KVM 2.1 on Linux 4.14 and provides 3-32% performance improvement for various file and I/O benchmarks.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2012.04a
• /
• pp.139-141
• /
• 2012

클라우드 시스템에서 사용되는 스토리지 서버는 다수의 워크로드가 혼재됨으로 인하여 상당수의 쓰기 연산이 Small Random한 특성을 가지게 된다. 좀 더 높은 성능을 위해서 이런 특성에 적합한 스토리지 서버를 구축하는 것이 필요하며 이를 위해 본 논문에서는 자주 사용되는 스토리지 프로토콜인 NFS와 iSCSI를 비교하여 어떤 쪽이 Small Random Write에 더 적합한지 실험을 통해 알아 보았다. 결과적으로 Small Random Write들은 캐시에 합쳐지는 효과에 상당한 영향을 받으며, 이런 캐시 효과가 더 효율적인 것은 iSCSI 임을 확인하였다.

• Journal of the Semiconductor & Display Technology
• /
• v.23 no.1
• /
• pp.65-70
• /
• 2024

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.

• KIISE Transactions on Computing Practices
• /
• v.21 no.1
• /
• pp.88-93
• /
• 2015

In modern computer systems, DRAM is commonly used as main memory due to its low read/write latency and high endurance. However, DRAM is volatile memory that requires periodic power supply (i.e., memory refresh) to sustain the data stored in it. On the other hand, PCM is a promising candidate for replacement of DRAM because it is non-volatile memory, which could sustain the stored data without memory refresh. PCM is also available for byte-addressable access and in-place update. However, PCM is unsuitable for using main memory of a computer system because it has two limitations: high read/write latency and low endurance. To take the advantage of both DRAM and PCM, a hybrid main memory, which consists of DRAM and PCM, has been suggested and actively studied. In this paper, we propose a novel page replacement algorithm for hybrid main memory. To cope with the weaknesses of PCM, our scheme focuses on reducing the number of PCM writes in the hybrid main memory. Experimental results shows that our proposed page replacement algorithm reduces the number of PCM writes by up to 80.5% compared with the other page replacement algorithms.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.3
• /
• pp.336-340
• /
• 2010

Flash storages are prevalent as portable storage in computing systems. When we consider the detachability of Flash storage devices, data integrity becomes an important issue. To assure extreme data integrity, file systems synchronously write all file data to storage accompanying hot write references. In this study, we concentrate on the effect of hot write references on Flash storage, and we consider the effect of absorbing the hot write references via nonvolatile write cache on the performance of the FTL schemes in Flash storage. In 80 doing, we quantify the performance of typical FTL schemes for workloads that contain hot write references through a wide range of experiments on a real system environment. Through the results, we conclude that the impact of the underlying FTL schemes on the performance of Flash storage is dramatically reduced by absorbing the hot write references via nonvolatile write cache.

• Journal of KIISE:Computing Practices and Letters
• /
• v.14 no.5
• /
• pp.537-541
• /
• 2008

Log-Structured File System(LFS) is a disk based file system that is optimized for improving the write performance. LFS gathers dirty data in memory as long as possible, and flushes all dirty data sequentially at once. In a real system, however, maintaining dirty data in memory should be flushed into a disk to meet file system consistency issues even if more memory is still available. This synchronizations increase the cleaner overhead of LFS and make LFS to write down more metadata into a disk. In this paper, by adapting Non-volatile RAM(NV-RAM) we modifies LFS and virtual memory subsystem to guarantee that LFS could gather enough dirty data in the memory and reduce small disk writes. By doing so, we improves the performance of LFS by around 2.5 times than the original LFS.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06a
• /
• pp.288-289
• /
• 2012

이 논문에서는 Solid State Drives(SSD)의 구조적인 특성을 활용한 Native Command Queueing(NCQ) 스케줄링 기법을 제안하려 한다. SSD는 Hard Disk Drives(HDD)와 달리 접근시간이 매우 짧고, 읽기/쓰기 속도가 서로 다르다는 특성이 있다. 그리고 SSD 내부에는 HDD와 마찬가지로 버퍼캐시가 존재한다. 이런 특성들을 활용하여 커맨드가 처리되는데 걸리는 시간을 모델링할 수 있다. 이렇게 모델링한 처리시간을 짧은 순서대로 스케줄링 정책에 적용하여 응답속도를 개선할 수 있다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.1
• /
• pp.1-10
• /
• 2010

Recently heterogeneous storage system such as hybrid hard disk drive (H-HDD) combining flash memory and magnetic disk is launched, according as the read performance of NAND flash memory is enhanced as similar to that of hard disk drive (HDD) and the power consumption of NAND flash memory is reduced less than that of HDD. However, the read and write operations of NAND flash memory are slower than those of rotational disk. Besides, serious overheads are incurred on CPU and main memory in the case that intensive write requests to flash memory are repeatedly occurred. In this paper, we propose the Least Frequently Used-Hot scheme that replaces the data blocks whose reference frequency of read operation is low and update frequency of write operation is high, and the data flushing scheme that rearranges the data blocks into the multi-zone of the rotation disk. Experimental results show that the execution time of the proposed method is 38% faster than those of conventional LRU and LFU block replacement schemes in I/O performance aspect and the proposed method increases the life span of Non-Volatile Cache 40% higher than those of conventional LRU, LFU, FIFO block replacement schemes.

• Journal of KIISE
• /
• v.43 no.5
• /
• pp.524-530
• /
• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.12
• /
• pp.913-917
• /
• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.