• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1124-1131
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• 2008

In this paper, we propose a timing synchronization scheme and its hardware architecture of the next generation IEEE 802.11n wireless LAN standard which is based on MIMO-OFDM technique. Proposed timing synchronization method takes two steps which consist of two modified auto-correlators. For coarse timing synchronization, a sliding window differentiator is used after a conventional auto-correlation in order to avoid plateau problem. The conjugate symmetry property of L-LTS is utilized for the simplification of fine timing synchronization. Since cross-correlation based methods are not required, the computational complexity and the number of multipliers can be reduced. In order to reduce the hardware complexity, we have used sign multipliers. Based on simulation results, the proposed method outperforms a conventional method. The proposed scheme can be applied to IEEE 802.11n systems and can easily be expanded to frequency synchronization scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.73-81
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• 2012

In this paper, we propose a high-speed synchronization method for Digital Radio Mondiale (DRM) receivers. In order to satisfy the high-speed synchronization requirement of DRM receivers, the proposed method eliminate the initial sampling frequency synchronization process in conventional synchronization methods. In the proposed method, sampling frequency tracking is performed after integer frequency synchronization and frame synchronization. Different correlation algorithms are applied to detect the first frame of the Orthogonal Frequency Division Multiplexing (OFDM) demodulation symbol with sampling frequency offset (SFO). A frame detection algorithm that is robust to SFO is selected based on the performance analysis and simulation. Simulation results show that the proposed method reduces the time spent for initial sampling frequency synchronization even if SFO is present in the DRM signal. In addition, it is verify that inter-cell differential correlation used between reference cells is roubst to the effect of initial SFO.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.139-149
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• 2007

Asynchronous OFCDM(Orthogonal Frequency and Code Division Multiplexing) systems must have a cell search process necessarily unlike synch개nous systems. this process is hewn initial synchronization and a three-step cell search algorithm is performed for the initial synchronization in the following three steps: OFCDM symbol timing, i.e., Fast Fourier Transform(FFT) window timing is estimated employing guard interval (GI) correlation in the first step, then the frame timing and CSSC(Cell Specific Scrambling Code) group is detected by taking the correlation of the CPICH(Common Pilot Channel) based on the property yielded by shifting the CSSC phase in the frequency domain. Finally, the CSSC phase within the group is identified in the third step. This paper proposes a modification group code with two or three block of the conventional CPICH based cell search algorithm in the second step which offers MS(Mobile Station) complexity reductions. however, the effect of the reduction complexity leads to degradation of the performance therefore, look for combination to have the most minimum degradation. the proposed block type group code with suitable combinations is the nearly sane performance as conventional group code and has a complexity reduction that is to be compared and verified through the computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.4
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• pp.424-432
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• 2016

World's leading countries are developing next generation digital broadcasting system specifications to support UHDTV (ultra-high definition television) contents and other various services. In order to maximize the transmission capacity by using the bandwidth efficiently, most broadcasting systems adopt MIMO-OFDM. In distributed-MIMO systems, multiple transmit antennas are spatially separated and therefore result in multiple timing offsets. To overcome this problem, this paper proposes a technique using a null symbol to detect each individual signal from distributed transmit antennas. By inserting null symbols before preambles, the receiver can distinguish the signals between each transmit antennas and perform frame synchronization. When the reception time difference is shorter than 500 samples, the proposed method outperforms the conventional method.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.1-8
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• 1998

This paper presents an asynchronous DS/CDMA multiuser detector, which is a two stage, symbol-by-symbol scheme consisting of conventional detectors followed by linear decorrelating detectors. The conventional detector first makes temporal decisions and the detected symbols are delayed by one symbol period to be used for the selection of decorrelating bases in the subsequent decorrelaing detection stage. It also employs a bank of early-late correlators in place of a bank of single correlators taking the small offset of chip timing asynchronism into account. The proposed detector requires only the coarse knowledge of relative time delays of interfering users and is suitable for digital implementation. To verify the detector performance, the analytical BER performance will be given and compared with the simulation results for BPSK DS/CDMA signals in AWGN channel. While the performance of the proposed detector will be analyzed for time-limited signal, the simulation is carried out for both the time-limited and band-limited signals. As can be seen in the simulation results, the proposed scheme shows good results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.34-42
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• 2005

In orthogonal frequency-division multiple access (OFDMA) uplink environments, asynchronously received signals can cause multiple access interference (MAI). This paper focuses on the performance degradation due to the MAI over frequency-selective fading channels. We first introduce the timing misalignment, which is defined as the relative timing difference between asynchronous timing error of uplink user and reference time of the base station, and analytically derive the MAI using the power delay profile of wide-sense stationary uncorrelated scattering (WSSUS) channel model. Then, the effective signal-to-noise ratio (SNR) and the average symbol error probability (SEP) are derived. The proposed analytical results are verified through simulations with respect to the region of the timing misalignment and the number of asynchronous users.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.243-245
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• 2014

본 논문에서는 OFDM(Orthogonal Frequency Division Multiplexing)시스템에서 OFDM 심벌 타이밍 옵셋에 따른 4096QAM 의 uncoded-BER(Bit Error Rate) 및 성상도를 측정하였다. uncoded-BER 은 수신기의 FEC(Forward Error Correction) 복호기 이전에서 측정된 BER 을 의미한다. 측정을 위해, OFDM 을 사용하는 DVB-C2(Digital Video Broadcasting for Cable Systems 2) 송수신기를 FPGA(Field Programmable Gate Array)를 이용하여 구현하였으며, OFDM 심벌의 CP(Cyclic Prefix)를 이용하여 OFDM 심벌 동기를 수행하였다. 일반적으로, OFDM 심벌 동기는 OFDM 심벌에서 CP 가 반복된다는 특성을 이용한 상관기를 사용한다. 또한, ISI(Inter Symbol Interference) 및 ICI(Inter Channel Interference)를 최소화하기 위해, 채널의 최대 지연시간을 고려하여 CP 내에서 OFDM 심벌 동기가 획득된다. 이럴 경우 수신기에서는 각 부반송파에 할당된 QAM 심벌들의 위상 회전이 발생하지만, 등화기에서 이러한 위상 회전이 보상된다. 부반송파에 할당된 파일롯 심벌들을 이용하여 채널 추정 및 보상을 하는 등화기에서, 파일롯 심볼들도 OFDM 심벌 타이밍 옵셋에 의해 위상회전이 발생하기 때문에 채널 추정 값에 영향을 미친다. 따라서, 본 논문에서는 4096QAM 과 ZF-LE(Zero Forcing Linear Equalizer)를 사용한 경우, OFDM 심벌 타이밍 옵셋에 따른 uncoded-BER 및 성상도의 측정 결과를 제시하였다.

• Journal of Satellite, Information and Communications
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• v.12 no.1
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• pp.125-131
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• 2017

In this paper, an efficient structure of device-to-device (D2D) synchronization preamble is proposed to meet the enhanced time and frequency synchronization requirements for D2D communication. D2D communication can be applied not only for the cellular communications, but also unmaned aerial vehicle communications and vehicle-to vehicle communication. The proposed preamble structure is transmitting signals at every odd subcarriers, and empty the other subcarriers to minimize the effect of inter-carrier interference. According to the simulation results, the proposed preamble structure provides improved time offset estimation performance, without degrading frequency offset estimation performance compared to the current LTE D2D preamble.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2016.11a
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• pp.63-65
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• 2016

DVB (Digital Video Broadcasting)-S2 (Satellite - Second Generation) 표준은 현재 위성방송 시스템으로 가장 많이 사용되고 있는 표준이나, 추가적인 성능향상과 보다 다양한 응용분야에 적용하기 위해 DVB-S2 기술을 확장한 DVB-S2x (Satellite - Second Generation Extension) 시스템이 제정되었다. 그 중에서도 612,540 심볼 길이의 수퍼프레임 (Super-frame) 구조를 선택적으로 도입하여 긴 데이터 길이에 대해 스크렘블링 (Scrambling)을 적용하는 방법과 PLS (Physical Layer Signaling) 코드와 같은 참조 데이터 필드를 반복적으로 사용하는 방법 등을 사용할 수 있도록 하였다. 이를 통해 동일채널 간섭 (co-channel interference)에 대한 강인성을 증가시키고, 매우 낮은 SNR (Signal to Noise Ratio) 환경에서의 수신기 성능 향상 효과를 제공하게 된다 본 논문에서는 버스트 슈퍼프레임 전송 기반의 DVB-S2x 수신기를 위한 동기부를 설계하고 구조를 제안한다. 슈퍼프레임의 포맷은 DVB-S2x Annex E 의 규격 중 2 번 포맷을 이용하였으며, 2 번 슈퍼프레임 포맷은 버스트 (burst) 기반의 전송 방식에 용이한 측면이 있다. 동기부는 크게 버스트 검출부, 주파수 복구부, 신호 이득 조절부 그리고 심벌 타이밍 복구부로 구성된다.