• Proceedings of the Korea Water Resources Association Conference
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• 2008.05a
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• pp.1727-1731
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• 2008

수자원의 효율적인 관리를 위해서는 신뢰성 있는 유량자료의 획득이 대단히 중요하다. 우리나라는 양질의 유량자료를 획득하기 위해 매년 많은 시간과 돈을 투자하고 있으나 자료의 질적인 면에서 만족할 만한 성과를 얻지 못하고 있다. 현재까지 우리나라의 유량자료는 댐의 수문자료와 수량관리 부처인 건교부에서 운영하는 수위표 지점의 수위-유량곡선에서 산출된 자료에 의존하고 있다. 그러나 수위-유량 관계식을 보정하기 위한 유량측정사업이 지속적이지 못하며, 이 관계식은 유량이 적은 저수기 및 갈수기에는 부정확하다는 한계가 있다. 또한, 국립환경과학원 낙동강물환경연구소에서 오염총량관리를 위한 낙동강수계 유량측정사업을 실시하고 있지만, 목적은 낙동강수계의 오염총량관리 단위유역 말단 47개 지점에서 유량측정을 효율적으로 실시하여 수질정책의 기초자료를 제공하는데 있다. 이 자료 역시 오염총량관리를 위하여 유량측정을 실시하여 수자원의 효율적인 관리를 위한 일 유량을 알 수가 없는 한계점을 가지고 있다. 따라서 저수기 및 갈수기에 수질정책의 기초자료를 제공하기 위해서 하천을 포함한 유역의 정확한 강우-유출특성의 파악이 필요하다. 그러나 강우-유출특성 또한 유역 내 강우의 시 공간적 분포가 다르며 그 자가 비선형성이 강하고 여러 변동성을 포함하므로, 강우로부터 하천의 유출량의 정확한 해석이 불가능하다. 그러나 최근 인공지능 분야에서 신호처리, 지능제어 및 패턴인식 등의 수단으로 사용되고 있는 신경망은 학습이라는 최적화 과정을 통해 입력과 출력으로 구성되는 하나의 시스템을 비선형적으로 구축할 수 있으며 이러한 이점을 활용하여 수자원 분야에서 다양하게 적용되고 있다. 본 연구의 목적은 강우-유출자료 및 댐 방류량 자료의 비선형적인 특정을 가장 잘 반영할 수 있는 신경망모형을 적용하여 수질정책의 기초자료를 제공하기 위하여 신뢰성 있는 유량자료를 산정하는 모형을 개발하는 것이다. 이를 위해서 낙동강물환경연구소에서 오염총량관리를 위한 낙동강수계 유량측정 지점 상류의 댐 방류량의 일 방류량자료와 강우자료를 입력 자료로 하여 유량을 예측할 수 있는 유량예측 신경망 모형 FFBN(Flow Forecasting By Neural)을 개발하였다. 그리고 입력 자료로서 장기유출모형인 SWAT의 모의결과를 입력 자료로 추가한 FFBNS(Flow Forecasting By Neural and SWAT)을 개발하였다. 신경망 모형의 구조는 입력층과 출력층 사이에 하나의 은닉층이 존재하는 다층 신경망으로 구성하였으며, 학습단계에서는 오류 역전파 알고리듬 학습방법 중 모멘텀법을 사용하였다. 예측된 유출량을 실측치와의 비교를 위하여 낙본D지점과 낙본 E지점에 대하여 $2005{\sim}2006$년까지의 모의 결과를 낙동 수위측정지점과 구미 수위측정지점의 실측치 통하여 복잡한 비선형성을 가지는 유출 시계열 자료에 대한 효과적인 최적의 신경망모델을 개발하여 유량을 예측하고 적용 가능성을 검토하고자 한다. 모의 결과는 수질정책의 기초자료 제공에 기여할 수 있을 것으로 판단된다.

• Journal of Broadcast Engineering
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• v.14 no.6
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• pp.749-768
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• 2009

In this paper, an intra prediction offset compensation method is proposed to improve intra prediction in H.264/AVC. In H.264/AVC, intra prediction based on various directions improves the coding efficiency by removing spatial correlation between neighboring blocks. In details, neighboring pixels in reconstructed block can be used as intra reference block for the current block to be coded when intra prediction method is used. In order to reduce further the prediction error of the intra reference block, the proposed method introduces an intra prediction offset which is determined in the sense of the rate-distortion optimization and is added to the conventional intra prediction block. Besides the intra prediction offset compensation, the coefficient thresholding method which is used for inter coding in JM 11.0, is used for chroma component in intra block, which leads the improvement of the luma coding efficiency of the proposed method. In experiments, we show that the proposed method achieves average 2.45% in High Profile condition and maximum 4.41% of bitrate reduction relative to JM 11.0.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.174-179
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• 2013

This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.259-268
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• 2014

In this paper, we suggest a method of extracting circuit parameters of the insulating transformer using S-parameter measurement, especially in high frequency range. At 60 Hz, conventionally, no load test and short circuit test are used to extract the circuit parameters. In this paper S-parameters measured from VNA(Vector Network Analyzer) were used to extract the transformer parameters using data fitting method (optimization). The S-parameters from the equivalent circuit using the extracted parameters showed good agreement with those from measurement. Furthermore, the transformer secondary voltages from the equivalent circuit model also coincide quite exactly to the measured secondary voltages in sinusoidal forms. Finally we assert that the proposed method to extract the parameters for the insulating transformer using S-parameter is valid especially in high frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.78-89
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• 1999

Previous wavelet network structures are determined by considering the relationship between wavelet windows distribution of training patterns that are transformed into time-frequency space. Because it is separated two algorithms that determines wavelet network structure and that modifies parameters of network, learning process that minimizes output error of network is executed after the network structure is determined. But this method has some weakness that training patterns must be transformed into time-frequency space by additional preprocessing and the network structure should be fixed during learning process. In this paper, we propose a new constructing method for wavelet network structure by using differences between the output and the desired response without preprocessing. Because the algorithm perform network construction and error minimizing process simultaneously, it can determine the number of hidden nodes adaptively as with the complexity of problems. In addition, the network structure is optimized by inserting new hidden nodes in the area that has maximum error and extracting hidden nodes that has no effect to the output of network. This algorithm has no constraint condition that all training patterns must be known, because it removes preprocessing procedure for training patterns and it can be applied effectively to systems that has time varying outputs.

• Journal of the Korean Society of Radiology
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• v.9 no.5
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• pp.307-314
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• 2015

This study was conducted in reducing the involuntary motion artifacts because of lungs and heart movements as well as the aliasing artifacts generated during the use of the reduced-FOV EPI technique while performing breast MRI. Performed on a total of 38 obesity female subjects who visited the clinic for pre-examination before surgery within the period from August 1 to November 30, 2014. The 3.0T MRI scanner equipped with a breast scanning coil. Qualitative and quantitative analyses were each used for the evaluation of the acquired images while an Paired T-test and Wilcoxon rank test were performed to check the statistical significance. The variation ratio rose by 15.69% with the additional application of a pre-saturation pulse in the lesion, by 13.72% near the lesion, and 20.63% in the fat and the contrast-to-noise ratio rose by 10.58% in and near the lesion and by 12.03% in the lesion and fat, respectively. there were increases of 22.05% and 21.42% at 0 and 1000 respectively in qulitative evaluation and growth of 16.10% in apparent diffusion coefficient. it showed a statistically significant result(p<0.05) in signal to noise ratio, contrast to noise ratio, diffusion slope coefficient and apparent diffusion coefficient. The involuntary movements artifacts that occur in the phase encoding direction and the aliasing artifacts are considered to be reduced to obtain the best image in the additional use of the pre-saturation pulse as DWI is acquired.

• Journal of the Korean Society of Radiology
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• v.14 no.3
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• pp.211-220
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• 2020

High-quality computed tomography (CT) images enable precise lesion detection and accurate diagnosis. A lot of studies have been performed to improve CT image quality while reducing radiation dose. Recently, deep learning-based techniques for improving CT image quality have been developed and show superior performance compared to conventional techniques. In this study, a super-resolution convolutional neural network (SRCNN) model was used to improve the spatial resolution of CT images, and image quality according to the hyperparameters, which determine the performance of the SRCNN model, was evaluated in order to verify the effect of hyperparameters on the SRCNN model. Profile, structural similarity (SSIM), peak signal-to-noise ratio (PSNR), and full-width at half-maximum (FWHM) were measured to evaluate the performance of the SRCNN model. The results showed that the performance of the SRCNN model was improved with an increase of the numbers of epochs and training sets, and the learning rate needed to be optimized for obtaining acceptable image quality. Therefore, the SRCNN model with optimal hyperparameters is able to improve CT image quality.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.29-45
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• 2017

Ad hoc sensor network is characterized by decentralized structure and ad hoc deployment. Sensor networks have all basic features of ad hoc network except different degrees such as lower mobility and more stringent energy requirements. Existing protocols provide different tradeoffs among some desirable characteristics such as fault tolerance, distributed computation, robustness, scalability and reliability. wireless protocols suggested so far are very limited, generally focusing on communication to a single base station or on aggregating sensor data. The main reason having such restrictions is due to maximum lifetime to maintain network activities. The network lifetime is an important design metric in ad hoc networks. Since every node does a router role, it is not possible for other nodes to communicate with each other if some nodes do not work due to energy lack. In this paper, we suggest an experimental ad-hoc on-demand distance vector routing protocol to optimize the communication of energy of the network nodes.The load distribution avoids the choice of exhausted nodes at the route selection phase, thus balances the use of energy among nodes and maximizing the network lifetime. In transmission control phase, there is a balance between the choice of a high transmission power that lead to increase in the range of signal transmission thus reducing the number of hops and lower power levels that reduces the interference on the expense of network connectivity.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.