• Title/Summary/Keyword: 신호 최적화

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Gate-Bias Control Technique for Envelope Tracking Doherty Power Amplifier (Envelope Tracking 도허티 전력 증폭기의 Gate-Bias Control Technique)

  • Moon, Jung-Hwan;Kim, Jang-Heon;Kim, Il-Du;Kim, Jung-Joon;Kim, Bum-Man
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.8
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    • pp.807-813
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    • 2008
  • The gate-biases of the Doherty power amplifier are controlled to improve the linearity performance. The linearity improvement mechanism of the Doherty amplifier is the harmonic cancellation of the carrier and peaking amplifier at the output power combining point. However, it is difficult to cancel the harmonic power for the broader power range because the condition for cancelling is varied by power. For the linearity improvement, we have explored the linearity characteristic of the Doherty amplifier according to the input power and gate biases of the carrier and peaking amplifier. To extend the region of harmonic power cancellation, we have injected the proper gate bias to the carrier and peaking amplifier according to the input power levels. To validate the linearity improvement, the Doherty amplifier is designed using Eudyna 10-W PEP GaN HEMT EGN010MKs at 2.345 GHz and optimized to achieve a high linearity and efficiency at an average output power of 33 dBm, backed off about 10 dB from the $P_{1dB}$. In the experiments, the envelope tracking Doherty amplifier delivers a significantly improved adjacent channel leakage ratio performance of -37.4 dBc, which is an enhancement of about 2.8 dB, maintaining the high PAE of about 26 % for the WCDMA 1-FA signal at an average output power of 33 dBm. For the 802.16-2004 signal, the amplifier is also improved by about 2 dB, -35 dB.

Performance Evaluation, Optimal Design and Complex Obstacle Detection of an Overlapped Ultrasonic Sensor Ring (중첩 초음파 센서 링의 성능 평가, 최적 설계 및 복합 장애물 탐지)

  • Kim, Sung-Bok;Kim, Hyun-Bin
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.4
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    • pp.341-347
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    • 2011
  • This paper presents the performance evaluation. optimal design. and complex obstacle detection of an overlapped ultrasonic sensor ring by introducing a new concept of effective beam width. It is assumed that a set of ultrasonic sensors of the same type are arranged along a circle of nonzero radius at regular spacings with their beams overlapped. First, the global positional uncertainty of an overlapped ultrasonic sensor ring is expressed by the average value of local positional uncertainty over the entire obstacle detection range. The effective beam width of an overlapped ultrasonic sensor ring is assessed as the beam width of a single ultrasonic sensor having the same amount of global positional uncertainty, from which a normalized obstacle detection performance index is defined. Second. using the defined index, the design parameters of an overlapped ultrasonic sensor ring are optimized for minimal positional uncertainty in obstacle detection. For a given number of ultrasonic sensors, the optimal radius of an overlapped ultrasonic sensor ring is determined, and for a given radius of an overlapped ultrasonic sensor ring, the optimal number of ultrasonic sensors is determined. Third, the decision rules of positional uncertainty zone for multiple obstacle detection are provided based on the inequality relationships among obstacle distances by three adjacent ultrasonic sensors. Using the provided rules, the obstacle outline detection is performed in a rather complex environment consisting of several obstacles of different shapes.

Implementation of the AMBA AXI4 Bus interface for effective data transaction and optimized hardware design (효율적인 데이터 전송과 하드웨어 최적화를 위한 AMBA AXI4 BUS Interface 구현)

  • Kim, Hyeon-Wook;Kim, Geun-Jun;Jo, Gi-Ppeum;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.15 no.2
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    • pp.70-75
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    • 2014
  • Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

Wide-area Surveillance Applicable Core Techniques on Ship Detection and Tracking Based on HF Radar Platform (광역감시망 적용을 위한 HF 레이더 기반 선박 검출 및 추적 요소 기술)

  • Cho, Chul Jin;Park, Sangwook;Lee, Younglo;Lee, Sangho;Ko, Hanseok
    • Korean Journal of Remote Sensing
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    • v.34 no.2_2
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    • pp.313-326
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    • 2018
  • This paper introduces core techniques on ship detection and tracking based on a compact HF radar platform which is necessary to establish a wide-area surveillance network. Currently, most HF radar sites are primarily optimized for observing sea surface radial velocities and bearings. Therefore, many ship detection systems are vulnerable to error sources such as environmental noise and clutter when they are applied to these practical surface current observation purpose systems. In addition, due to Korea's geographical features, only compact HF radars which generates non-uniform antenna response and has no information on target information are applicable. The ship detection and tracking techniques discussed in this paper considers these practical conditions and were evaluated by real data collected from the Yellow Sea, Korea. The proposed method is composed of two parts. In the first part, ship detection, a constant false alarm rate based detector was applied and was enhanced by a PCA subspace decomposition method which reduces noise. To merge multiple detections originated from a single target due to the Doppler effect during long CPIs, a clustering method was applied. Finally, data association framework eliminates false detections by considering ship maneuvering over time. According to evaluation results, it is claimed that the proposed method produces satisfactory results within certain ranges.

Analyses on the Performance of the CNN Reflecting the Cerebral Structure for Prediction of Cybersickness Occurrence (사이버멀미 발생 예측을 위한 대뇌 구조를 반영한 CNN 성능 분석)

  • Shin, Jeong-Hoon
    • Journal of the Institute of Convergence Signal Processing
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    • v.20 no.4
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    • pp.238-244
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    • 2019
  • In this study, we compared and analyzed the performance of each Convolution Neural Network (CNN) by implementing the CNN that reflected the characteristics of the cerebral structure, in order to analyze the CNN that was used for the prediction of cybersickness, and provided the performance varying depending on characteristics of the brain. Dizziness has many causes, but the most severe symptoms are considered attributable to vestibular dysfunction associated with the brain. Brain waves serve as indicators showing the state of brain activities, and tend to exhibit differences depending on external stimulation and cerebral activities. Changes in brain waves being caused by external stimuli and cerebral activities have been proved by many studies and experiments, including the thesis of Martijn E. Wokke, Tony Ro, published in 2019. Based on such correlation, we analyzed brain wave data collected from dizziness-inducing environments and implemented the dizziness predictive artificial neural network reflecting characteristics of the cerebral structure. The results of this study are expected to provide a basis for achieving optimal performance of the CNN used in the prediction of dizziness, and for predicting and preventing the occurrence of dizziness under various virtual reality (VR) environments.

Evaluation of Image Quality and Stability of Radiation Output according to Change in Tube Voltage and Sensitivity when Abdomen and Pelvis Examination of Digital Radiography (DR) (디지털 방사선 시스템(DR)의 복부와 골반부 검사 시 관전압과 감도 변화에 따른 영상 화질과 방사선 출력의 안정성 평가)

  • Hwang, Jun-Ho;Yang, Hyung-Jin;Choi, Ji-An;Lee, Kyung-Bae
    • The Journal of the Korea Contents Association
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    • v.19 no.12
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    • pp.517-526
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    • 2019
  • The purpose of this study is to find the optimal method for clinical application by analyzing image quality and radiation output according to parameter combination when using the Automatic Exposure Control (AEC). The experimental method combines 70, 81 kVp with sensitivity S200, S400, S800 and S1000 of the Automatic Exposure Control for Entrance Surface Dose (ESD), current volume, Signal to Noise Ratio (SNR), Contrast to Noise Ratio (CNR), Time-to-Radiation Dose Curve in abdomen and pelvis. And then, image quality and radiation output stability were evaluated. As a results, Entrance Surface Dose, current volume, Signal to Noise Ratio, Contrast to Noise Ratio decreased as the tube voltage and sensitivity were set higher. In addition, the higher tube voltage and sensitivity, the Time-to-Radiation Dose Curve showed a poor output stability. In conclusion, the higher the combination of tube voltage and sensitivity in the use of Automatic Exposure Control, the more problems can be seen in image quality and stability of the radiation output. Therefore, a relatively low combination of tube voltage and sensitivity showed that the image quality and radiation output stability could be optimized by minimizing the error range that would occur when the detector recognized a combination of parameters.

A 12b 100MS/s 1V 24mW 0.13um CMOS ADC for Low-Power Mobile Applications (저전력 모바일 응용을 위한 12비트 100MS/s 1V 24mW 0.13um CMOS A/D 변환기)

  • Park, Seung-Jae;Koo, Byeong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.56-63
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    • 2010
  • This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

Synchronization performance optimization using adaptive bandwidth filter and average power controller over DTV system (DTV시스템에서 평균 파워 조절기와 추정 옵셋 변화율에 따른 대역폭 조절 필터를 이용한 동기 성능 최적화)

  • Nam, Wan-Ju;Lee, Sung-Jun;Sohn, Sung-Hwan;Kim, Jae-Moung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.5
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    • pp.45-53
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    • 2007
  • To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

A Parametric Study of Pulsed Gamma-ray Detectors Based on Si Epi-Wafer (실리콘 에피-웨이퍼 기반의 펄스감마선 검출센서 최적화 연구)

  • Lee, Nam-Ho;Hwang, Young-Gwan;Jeong, Sang-Hun;Kim, Jong-Yeol;Cho, Young
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.7
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    • pp.1777-1783
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    • 2014
  • In this paper, we designed and fabricated a high-speed semiconductor sensor for use in power control devices and analyzed the characteristics with pulsed radiation tests. At first, radiation sensitive circular Si PIN diodes with various diameters(0.1 mm ~5.0 mm) were designed and fabricated using Si epitaxial wafer, which has a $42{\mu}m$ thick intrinsic layer. The reverse leakage current of the diode with a radius of 2 mm at a reverse bias of 30 V was about 20.4 nA. To investigate the characteristic responses of the developed diodes, the pulsed gamma-radiation tests were performed with the intensity of 4.88E8 rad(Si)/sec. From the test results showing that the output currents and the rising speeds have a linear relationship with the area of the sensors, we decided that the optimal condition took place at a 2 mm diameter. Next, for the selected 2 mm diodes, dose rate tests with a range of 2.47E8 rad(Si)/sec to 6.21E8 rad(Si)/sec were performed. From the results, which showed linear characteristics with the radiation intensity, a large amount of photocurrent over 60mA, and a high speed response under 350ns without saturation, we can conclude that the our developed PIN diode can be a good candidate for the sensor of power control devices.

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems (고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기)

  • Han, Jae-Yeol;Kim, Young-Ju;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.77-85
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    • 2008
  • This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.