• Bulletin of the Korean Space Science Society
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• 1993.04a
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• pp.22-22
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• 1993

천체 B-선 관측용으로 많이 이용되고 있는 X-선 비례계수관을 실험실형으로 재작하고 그 특성을 조사하였다. X-선 검출기의 구조는 10 $\times$ 20 $\times$ 2cm3 인 검출체적내에 10개의 전극선이 설치되어있는 다중선 비례계수관이며, 검출가스로서 Argon(90%) + CH4 (10%)인 g혼합가스를 사용하였다. 이러한 구조에서 5.9 keV에 대한 에너지 분해능은 16%를 얻었으나, 정상적인 전극연결방법에서는 검출기 끝측에 위치한 전극에서 생기는 electric field 변형매문에, 양극선 배열방향에서 조정된 이득의 군일성이 나쁘게 나타났다. 따라서 다중선들의 각 전극선에 전압보상법(voltage compansation method)을 적용하여 검출기 전반에 걸친 이득의 균일성을 2 % (rms 값) 이내로 보정할 수 있었다. 아울러 신호처리회로 중 에너지분석을 위한 파고분석기, 비 X-선 재거를 위한 상승시간선별기(rise-time discriminator)등을 제작하였으며 이들을 이용한 전반적인 신호처리회로의 구성에 대하여 논하고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.382-385
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• 1996

디지탈 신호처리에 혼돈 신호를 적용하기 위해 선형 확산 결함(coupled linear diffusion)을 이용하여, 궤도 (trajectory)의 혼돈적인 고유특성은 변함이 없고 주파수 만 체배관계에 있는 4가지 혼돈 신호들을 발생시켰다. 혼돈 신호들을 발생시키기 위한 기본 혼돈 회로로는 Chua 회로를 사용하였고, 이 혼돈 신호들을 복극 4레벨 방식에 응용하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.249-252
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog to comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an exective isolation strategy for removing noise and signal coupling of each sensor pixel. The 128$\times$144 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of Radiation Protection and Research
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• v.37 no.1
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• pp.16-24
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• 2012

In the present study, a gamma-ray detector and associated signal processing circuit was developed for a side-absorber of a dual-mode Compton camera. The gamma-ray detector was made by optically coupling a CsI(Tl) scintillation crystal to a silicon photodiode. The developed signal processing circuit consists of two parts, i.e., the slow part for energy measurement and the fast part for timing measurement. In the fast part, there are three components: (1) fast shaper, (2) leading-edge discriminator, and (3) TTL-to-NIM logic converter. AC coupling configuration between the detector and front-end electronics (FEE) was used. Because the noise properties of FEE can significantly affect the overall performance of the detection system, some design criteria were presented. The performance of the developed system was evaluated in terms of energy and timing resolutions. The evaluated energy resolution was 12.0% and 15.6% FWHM for 662 and 511 keV peaks, respectively. The evaluated timing resolution was 59.0 ns. In the conclusion, the methods to improve the performance were discussed because the developed gamma-ray detection system showed the performance that could be applicable but not satisfactory in Compton camera application.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• 대한방사선방어학회:학술대회논문집
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• 2011.11a
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• pp.122-123
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• 2011

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2551-2553
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• 2000

고속 신호처리 및 실시간 제어 분야에 적합한 제어성능을 발휘하기 위해서는 신호처리전용 마이크로프로세서인 DSP(Digital Signal Processor)를 이용한 제어용 보드가 널리 활용되고 있다. 본 연구를 통하여 전기도금용 전원장치의 고성능화를 위하여 DSP제어용 보드를 개발하였으며, 전체구성은 고속 신호처리를 위한 메인 마이크로프로세서로서 경제성과 응용범위가 넓은 TMS320C32 DSP CHIP, Wait없는 프로그램 및 데이터 처리를 위한 고속 SRAM, 외부 디지털 입출력을 위한 인터페이스 회로, 아나로그 입출력 회로 및 PC 혹은 다른 마이크로컴퓨터와의 통신을 위한 직렬 통신 회로 등으로 구성하였다. 개발된 DSP 보드는 시제품 제작을 완료하여 그 성능 및 신뢰성을 검증하였으며, 전기도금장치의 고성능 제어처리를 위하여 채용하여 상품화 개발을 완료하였다.

• Journal of radiological science and technology
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• v.35 no.4
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• pp.315-319
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• 2012

The aim of this study was to develop a signal process circuit for a position sensitive avalanche photodiode detector. The circuit parts consisted of amplification, differential and peak/hold circuit. This research was the baseline to develop highly compact radiation detector. The signal was amplified by an amplification chip and its shape was changed in a differential circuit to minimize the pulse tailing. The peak/hold circuit detect the peak of the signal from the differential circuit and hold the amplitude of the peak for data acquisition. In order to test the intrinsic function of the circuit, the input signal was transmitted from a commercial pulse generator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1297-1303
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling, ESD of each sensor pixel. The 128${\times}$l44 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.197-200
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• 2003

본 논문에서는 IEEE 802.11a 무선 LAN 용 CODEC 회로를 설계하고, VHDL 코딩과 FPGA에 의한 회로설계 검증에 관해 기술한다. IEEE 802.lla WLAN CODEC의 구조는 크게 데이터 보호를 위한 스크램블러/디스크램블러, 채널 에러에 대한 정보보호를 위한 Convolutional 부호기와 Viterbi 복호기로 구성된 채널 코덱, 그리고 연집에러를 랜덤 에러로 변화시키는 인터리버/디인터리버로 구성된다. 본 논문에서는, 이와 같은 CODEC의 각 부분을 하드웨어로 구현하기 위한 새로운 회로구성을 제안하고, 그 성능을 VHDL 코딩에 의한 시뮬레이션과 FPGA에 의한 하드웨어 검증 결과를 제시한다.