• Proceedings of the Korean Society of Computer Information Conference
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• 2015.07a
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• pp.193-195
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• 2015

본 연구에서는 시스템 내부에 존재하는 불확실성에 대하여 안정성을 만족하는 입력신호 V, I, R, PWM의 신호를 사용자가 선택하는 신호로 변환하여 출력할 수 있는 신호변환기의 성능 및 설계방법을 연구 한다. 본 연구에서는 시간지연이 존재하는 신호변환기를 안정된 입/출력을 수행하여 나타나는 V, I, R, PWM 신호의 시간지연의 영향을 고려한 설계와 그 성능을 평가해 보았다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.11-11
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• 2001

본 논문에서는 카운터와 커패시터를 사용하여 시간 정보로부터 디지털 출력 값을 얻을 수 있는 새로운 시간-디지털 변환기를 제안하였다. 기존의 시간-디지털 변환회로의 경우 디지털 출력 값을 얻기 위해서는 입력 신호가 인가된 후 입력 시간보다 더 긴 공정시간이 필요하였다. 또한 입력 신호의 시간 간격에 무관하게 카운터의 클럭 주파수가 일정하여 변환된 디지털 값의 분해도는 항상 일정하였다. 그러나 본 논문에서 제안한 시간-디지털 변환 회로는 입력 신호가 인가됨과 동시에 지연시간 없이 디지털 출력 신호를 얻을 수 있으며, 또한 수동소자의 값을 변화시킴으로서 원하는 입력 시간 영역과 분해도를 쉽게 구현할 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.10
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• pp.1282-1289
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• 2019

In order to measure the transfer characteristic(S21) of the impedance transformer, two impedance transformers must be symmetrically connected. However, the transfer characteristic of two symmetrically connected impedance transformers is influenced by the length of the intermediate connection line. This paper theoretically examines closely the length of the intermediate connection line to obtain the accurate transfer characteristic of the impedance transformer. The electrical length of the intermediate connection line for obtaining the accurate transfer characteristic of the 4:1(50-Ω:12.5-Ω) impedance transformer is calculated about 45°. Using the calculated length of the connection line, The λ/4-microstrip impedance transformer is fabricated at 1 GHz to measure the transfer characteristic. The symmetrically connected impedance transformer is measured the reflection characteristic(S11) of -40.64dB and the transfer characteristic(S21) of -0.154dB at 0.980GHz. This value is approximately equal to the theoretical calculated 987MHz center frequency and -0.15dB transfer loss value of the λ/4-microstrip impedance transformer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.