• The Journal of the Korea Contents Association
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• v.22 no.3
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• pp.81-93
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• 2022

The stock investing is one of the most popular investment techniques. However, since it is not easy to obtain a return through actual investment, various strategies have been devised and tried in the past to obtain an effective and stable return. Among them, the volatility breakout strategy identifies a strong uptrend that exceeds a certain level on a daily basis as a breakout signal, follows the uptrend, and quickly earns daily returns. It is one of the popular investment strategies that are widely used to realize profits. However, it is difficult to predict stock prices by understanding the price trend pattern of stocks. In this paper, we propose a method of buying and selling stocks by predicting the return in trading based on the volatility breakout strategy using a bi-directional long short-term memory deep neural network that can realize a return in a short period of time. As a result of the experiment assuming actual trading on the test data with the learned model, it can be seen that the results outperform both the return and stability compared to the existing closing price prediction model using the long-short-term memory deep neural network model.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.23 no.1
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• pp.109-117
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• 2011

It was calculated using empirical formulas for the weight of Tetrapod, which was a representative armor unit in the rubble mound breakwater in Korea. As the formulas were evaluated from a curve-fitting with the result of hydraulic test, the uncertainty of experimental error was included. Therefore, the neural network and M5' model tree were used to minimize the uncertainty and predicted the stability number of armor block. The index of agreement between the predicted and measured stability number was calculated to assess the degree of uncertainty for each model. While the neural network with the highest index of agreement have an excellent prediction capability, a significant disadvantage exists that general designers can not easily handle the method. However, although M5' model tree has a lower prediction capability than the neural network, the model tree is easily used by the designers because it has a good prediction capability compared with the existing empirical formula and can be used to propose the formulas like an empirical formula.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.237-240
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• 2012

This paper describes an implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-core supports three master key lengths of 128/192/256-bit specified in the standard and the four modes of operation including ECB, CBC, CTR and OFB. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. The ARIA crypto-core is verified by FPGA implementation, the estimated throughput is about 1.07 Gbps at 167 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.3
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• pp.256-261
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• 2010

In this paper, a new nonlinear predictor using general regression neural network(GRNN) is proposed for the subband coding of moving pictures. The performance of a proposed nonlinear predictor is compared with BMA(Block Match Algorithm), the most conventional motion estimation technique. As a result, the nonlinear predictor using GRNN can predict well more 2-3dB than BMA. Specially, because of having a clustering process and smoothing noise signals, this predictor well preserves edges in frames after predicting the subband signal. This result is important with respect of human visual system and is excellent performance for the subband coding of moving pictures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.