• Information and Communications Magazine
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• v.9 no.11
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• pp.47-52
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• 1992

신경망 실용화에 기본이 되는 신경망 VLSI 기술의 최근 발전 추세에 관하여 검토하였다. 대규모 고속 신경망 VLSI 구현 방법들인 디지털, 아날로그, 하이브리드 신경망 칩들을 비교하였으며, 십 수만 단위의 하이브리드 신경망 칩기술을 제시하였다.

• The KIPS Transactions:PartB
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• v.9B no.4
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• pp.429-436
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• 2002

In order to apply the artificial neural network to the practical application, it is needed to implement it with the hardware system. It is most promising to make it with the hybrid VLSI among various possible technologies. When we Implement a trained network into the hybrid neuro-chips, it is to be performed the process of the quantization on its neuron outputs and its weights. Unfortunately this process cause the network's outputs to be distorted from the original trained outputs. In this paper we analysed in detail the statistical characteristics of the distortion. The analysis implies that the network is to be trained using the normalized input patterns and finally into the solution with the small weights to reduce the distortion of the network's outputs. We performed the experiment on an application in the time series prediction area to investigate the effectiveness of the results of the analysis. The experiment showed that the network by our method has more smaller distortion compared with the regular network.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.46-54
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• 1999

The output values of cellular neural networks would have errors because they can be stabilized at local minimums depending on the initial states of each cell. So, in this paper, we design the $6\times6$cellular neural networks with annealing capability which guarantees that the outputs reaches the global minimum to have correct output values independent of the initial states of each cell. This chip is designed using a $0.8\mu\textrm{m}$ CMOS technology The designed chip contains about 15,000 transistors and the chip size is about $2.89\times2.89\textrm{mm}^2$. The simulation results of edge extraction and hole filling using the designed circuit show that the outputs values would have errors in un-annealed case, but not in annealed case. In the simulation, the annealing time of $3\musec$ is employed.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.3
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• pp.64-74
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• 2007

The continuous chip in turning operation deteriorates precision of workpiece and causes a hazardous condition to operator. Thus the chip form control becomes a very important task for reliable machining process. So, grooved chip breaker is widely used to obtain reliable discontinuous chip. However, developing new cutting insert having chip breaker takes long time and needs lots of research expense due to a couple of processes such as forming, sintering, grinding and coating of product and many different evaluation tests. In this paper, performance of commercial chip breaker is evaluated with neural network which is learned with a back propagation algorithm. For the evaluation, several important elements(depth of cut, land, breadth, radius) which directly influence the chip formation were chosen among commercial chip breakers and were used as input values of neural network. With the results of these input values, the performance evaluation method was developed and applied that method to the commercial tools.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06c
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• pp.399-402
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• 1994

본 논문에서는 국내에서 개발된 신경망 VLSI 인 URAN에 대하여 살펴보고 URAN을 이요한 DAM성 인식 시스템의 설계에 관해 기술한다. 시뮬레이션을 통해 낮은 정밀도의 입출력 및 연결강도, 선형 출력함수를 가지는 뉴런을 사용하는 신경망 음성 인식 시스템의 성능을 분석하고 잡음 환경에서 낮은 정밀도를 사용한 신경망의 성능 저하 정도를 검토한다.

• Journal of Korea Multimedia Society
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• v.4 no.3
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• pp.257-269
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• 2001

Because of increasing number of integrated circuit, there is many tries of making chip of neural network and some chip is exit. but this is not prefer because YLSI technology can't support so large hardware. So imitation of whole system of neural network is more prefer. There is common procedure in signal processing as in the neural network and pattern recognition. That is multiplication of large amount of signal and reading LUT. This is identical with some operation of MLP, and need iterative and large amount of calculation, so if we make this part with hardware, overall system's velocity will be improved. So in this paper, we design neutral network, not neuron which can be used to many other fields. We realize this part by following separated bits addition method, and it can be appled in the real time parallel process processing.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.12
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• pp.106-112
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• 1998

A major problem in automation of turning operations is the difficulty in obtaining a sufficient and reliable chip control. The chip should be detected in order to provide a optimum chip control for unmanned turning operation. Using the difference of energy radiated from the chip, chip Patterns are estimated using pyrometer. From the initial output from the pyrometer, chips are identified according to the backpropagation algorithm developed in the research. The learning system developed in this work can be applied in real-time control of turning process with minor modification in drive system.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.06a
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• pp.1237-1240
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• 1998

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.481-484
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• 2005

본 논문에서는 부동소수점 연산을 사용하면서도 빠른 처리속도를 가지는 신경망의 파이프라인 설계를 제안한다. 부동소수점 연산은 고정소수점 연산보다 느린 처리속도와 많은 면적으로 일반적인 하드웨어 구현에서 잘 사용되지 않지만, 제안된 구조에서는 고정소수점 연산보다 더 정확한 값을 계산할 수 있는 부동소수점 연산을 사용하며 부동소수점의 느린 처리 속도를 보완할 수 있도록 파이프라인 구조를 사용한다. 파이프라인 구조의 성능을 검증하기 위해 2 가지의 서로 다른 구조의 신경망을 사용한다. 실험 환경으로는 Xilinx XC2V8000 칩과 Xilinx ISE 6.2 의 합성 도구를 사용한다. 실험 결과는 파이프라인 구조일 때의 신경망은 각각 7 클럭, 8 클럭이 소요되고, 파이프라인 구조가 아닐 때 각각의 신경망은 77 클럭, 84 클럭으로써 파이프라인 구조일 때 약 10 배의 빠른 처리를 가진다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.993-997
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• 1997

The continuous chip depresses the accuracy of workpieces and promotes the wear of machine tools and hunts operators. So chip control os a major problem in turning process. In this paper, a method of chip identification is develope by pyrometer. The identifier is applied in real-time control of chip pattern with adjusting feedrate.