• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.3
• /
• pp.410-424
• /
• 1993

In this paper, we present new techniques for designing systolic arrya and asynchronous arrays for digital-signal processings. More specifically, we propose a systolic array with simple local interconnections which achieves optimal performance without having undesirable features such as preloading input data or global broadcasting. As asynchronous array for digital-signal processings, which can speed up the total computation time significantly is also which can speed up the total computation time significantly is also presented. The key component of the asynchronous array is a presented. The key component of the asynchronous array is a comunicaiton protocol which controls input data flow properly and efficiently. Finally, performance of the arrays is analyzed and a simulation using Occam programmed in a Transputer network is reported.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.8
• /
• pp.2222-2232
• /
• 1999

This paper proposed a Systolic Arrays architecture for computing edge detection on images. It is very difficult to be processed images to real time because of operations of local operators. Local operators for computing edge detection are to be used in many image processing tasks, involve replacing each pixel in an image with a value computed within a local neighborhood of that pixel. Computing such operators at the video rate requires a computing power which is not provided by conventional computer. Through computationally expensive, it is highly regular. Thus, this paper presents a systolic arrays for tasks such as edge detection and laplacian, which are defined in terms of local operators.

• The KIPS Transactions:PartA
• /
• v.11A no.2
• /
• pp.109-114
• /
• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.2
• /
• pp.145-154
• /
• 1999

본 논문에서는 주어진 문제의 루프 알고리즘으로부터 시스톨릭 어레이 구현이 용이한 정규 순환 방정식으로의 자동적 유도를 위한 대수적인 방법과 조건을 제시하였다. 이를 위하여 계산점 집합과 순차 정렬 벡터를 구하고, 행렬의 커널을 이용하여 자료 흐름 벡터를 찾았으며, 정규 파이프라이닝 가능성 조건을 제시하였다 그리고 각 계산점에 대한 배열 원소의 초기 입력 위치를 구하였다. 본 논문에서 제시된 방법을 사용하면 주어진 루프 알고리즘을 정규 순환방정식으로 자동적으로 유도 할 수 있으며, 주어진 알고리즘이 정규 순환 방정식으로 유도될 수 있는지를 검사할 수 있다.

• The KIPS Transactions:PartA
• /
• v.9A no.3
• /
• pp.281-286
• /
• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.