• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.2
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• pp.171-178
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• 2023

PCM data is result of air-vehicle flight test, this data is distributed for each engineers to analyze its condition. Since line-of-sight between the air-vehicle and the ground receiver cannot always be secured, remote PCM data recording system was claimed to be required. In this paper multi-function PCM data recorder has been described. This PCM data recorder was intended to place on inside of flight object. It can record about two hours in 32 GB SD card with maximum 7 Mbps data rate. RS-422/485 and RJ-45 interface enhanced accessibility for users. 5 V and 1 A power consumption and 19.5 mm × 152.5 mm × 102.3 mm allow to connect with mobile PCM devices. It acquired more than 190-minutes data in 12-times flight test. Also, it achieved military standard environmental test MIL-STD-810G to prove its stability and solidness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.36-45
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• 2005

This paper addresses the application of motor current spectral analysis for the detection of rolling-element bearing damage in induction machines. We set the experimental test bed. They is composed of the normal condition bearing system, the abnormal rolling-element bearing system of 2 type induction motors with shaft deflection system by external force and a hole drilled through the outer race of the shaft end bearing of the four pole test motor. We have developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current The effects on the stator current spectrum are described and related frequencies are also determined. This is an important result in the formulation of a fault detection scheme that monitors the stator currents. We utilized the FFT(Fast Fourier Transform), Wavelet analysis and averaging signal pattern by inner product tool to analyze stator current components. Especially, the analyzed results by inner product clearly illustrate that the stator signature analysis can be used to identify the presence of a bearing fault.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.793-795
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• 2011

In this paper, an wet diaper sensor system for u-healthcare is implemented and designed. The u-healthcare system of wet diaper sensor consists of sensor node, data-logger/gateway, and server or user terminals. The sensor node includes $NH_3$, humidity, and temperature sensors and TI CC2530 chip, and the data-logger/gateway can connect to a communication network and send the aggregated data from the sensor nodes to a server, and the server can manage the situation of the sensor node and make another analyzed information. Also user terminals can request and obtain the information necessary from the server. The algorithm for detecting wet diaper is proposed, and using the proposed algorithm, the sensitivity for detecting wet diaper is 100%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Journal of Biomedical Engineering Research
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• v.19 no.5
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• pp.477-486
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• 1998

In this paper, we implemented the urine analysis system capable of measuring a qualitative and semi-quantitative and assay using strip. The analysis algorithm of urine analysis was adopted a fuzzy logic-based classifiers that was robust to external error factors such as temperature and electric power noises. The spectroscopic properties of 9 pads In a strip were studied to developing the urine analysis system was designed for robustnesss and stability. The urine analysis system was consisted of hardware and software. The hardware of the urine analysis system was based on one-chip microprocessor, and Its peripherals which composed of optic modulo, tray control, preamplifier, communication with PC, thermal printer and operating status indicator. The software of the urine analysis system was composed of system program and classification program. The system program did duty fort system control, data acquisition and data analysis. The classification program was composed of fuzzy inference engine and membership function generator. The membership function generator made triangular membership functions by statical method for quality control. Resulted data was transferred through serial cable to PC. The transferred data was arranged and saved be data acquisition program coded by C+ + language. The precision of urine analysis system and the stability of fuzzy classifier were evaluated by testing the standard urine samples. Experimental results showed a good stability states and a exact classification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.