• Journal of KIISE:Computing Practices and Letters
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• v.15 no.7
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• pp.489-494
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• 2009

Since multimedia content is often independently encoded into multiple variations having diverse bandwidths, resolutions and compression formats, the same segment might be stored at different temporal positions within the variations. In this paper, we present a durable multimedia bookmark mechanism which provides a convenient way of switching to any variation before or during playback of the multimedia content, without experiencing temporal discontinuity or overlapping a portion of the content. We also present a new multimedia bookmark player with which users can manage a personal collection of bookmarks with an intuitive visual interface.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.37-41
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• 2018

In this paper, we evaluate the power consumption of IEEE802.15.4e TSCH which uses the specific link scheduling scheme proposed in reference[1]. And we also compares it with the power consumption of conventional single channel IEEE802.15.4. The power consumption of IEEE802.15.4e TSCH is smaller than the conventional one under the any conditions of traffic. The reasons can be explained as the followings. Firstly, TSCH does not have backoff time because of using the collision free link scheduling. Secondly, there is the timing difference of MAC offset parameter between TSCH and conventional IEEE802.15.4 Lastly, the devices in TSCH mode sleep during the time slots which are not assigned to itself.

• Journal of Broadcast Engineering
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• v.21 no.2
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• pp.261-267
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• 2016

In this paper, Method for the phase distortion compensation timing offset and DC eliminator for the pilot component estimation and removal, transmitted and received signal correlation in the delay scheme DAB interference cancellation based on the same channel for using for estimating the feedback signal based on a between for removal for the timing offset compensation It proposes a repeater. This was applied to the ATSC system. The on-channel repeater of the proposed interference cancellation based on the interference removing capability is improved in interference signal is 20dB greater than the primary transmission signal environment via the return channel estimation and improve performance RFP. Accordingly, it was confirmed by simulation that good signal is sent out with the improvement of the ability of the repeater.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.479-481
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• 2006

1967년 시간의 기본 단위인 초가 세슘원시계에 의해 정의된 이후, 각 국의 표준기관에서는 보다 정확한 원자시계개발 연구와 평가를 수행하고 있다. 이러한 연구는 정확한 시간척도(Time Scale)와 국제원자시를 생성하여 산업과 과학분야에 기여하기 위한 것이며, 이에 필연적으로 국제간 시각비교 개선을 위한 연구도 함께 발전되어 왔다. 전파를 이용한 시각비교는 지상파를 이용하던 70년대 초부터 시작되었는고 1981년부터 GPS에 의한 시각비교 방법이 소개된 이후, 80년대 후반에 들어서면서 GPS 활성화에 따라 급격히 시각비교 정확도가 향상되었다. 그러나 GPS와 더불어 통신위성을 이용한 양방향 시각비교(TWSTFT)의 필요성에 따라 세계 선진 표준기관들은 이 방법을 수행하고 있다. 한국표준과학연구원(KRISS)에서도 통신위성을 이용한 양방향시각비교를 구축하여 운용하고 있으며 아시아, 오세아니아, 유럽지역과 비교를 할 수 있는 시스템을 구축하여 운용하고 있다. 본 논문에서는 PAS-8위성을 이용한 KRISS와 NMIA(호주)와 양방향시각비교를 수행함에 있어 필수적으로 계산 또는 측정하여야하는 오프셋값을 결정방법으로 GPS와 Circular-T를 이용하여 산출한 결과를 제시한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.476-482
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• 2014

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.8
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• pp.3053-3059
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• 2010

In DS-CDMA method, Mobile Stations own jointly one radio channel and are made to use a PN code (Pseudo-Noise Code) for the purpose of minimize interference. However, corelation value of PN code is one when time delay is zero but the corelation value is 1 / N when time delay is not 0. Therefore corelation characteristic does not fully attained. As a result, when the user increase, the performance degradation and system capacity problem will be able to occur by interference among users. In this paper, the PN code has ideally self corelation. It was proved that PN code could depress interference from other users in multiple access system.