• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4B
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• pp.224-231
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• 2008

EPONs are a low cost, high speed solution to the bottleneck problem of broadband access networks. To support point-to-point and shared LAN emulation, EPONs use the multi-point control protocol (MPCP), which uses logical link identification (LLID) for frame tagging and filtering between the OLT and ONUs. In this paper, ONU-based multicast or multiple shared LAN emulation is used for IPTV channel package delivery services. Using ONU-based VLAN services, EPONs can support separate and secure connections between providers and subscribers in a simple manner. Also, IPTV channel packages can be delivered through EPONs by implementing ONU-based VLAN and IGMP snooping mechanisms. By showing fast channel zapping time of proposed architecture, I show that EPONs is suitable for IPTV channel package delivery service.

• Journal of Institute of Control, Robotics and Systems
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• v.1 no.1
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• pp.63-70
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• 1995

퍼지논리제어기는 산업응용에 광범위하게 연구되고 있으며, 계속적으로 사용되고 있다. 그러나 퍼지집합의 조정을 통해 최적규칙을 구축하기 위하여, 시행착오에 의한 매우 능숙한 기술이 요구된다. 이 논문에서는 첫째로, 퍼지논리제어기와 기존의 PID 제어기로 구성된 하이브리드 퍼지제어기를 제안한다. 즉, 시스템의 제어 입력은 퍼지변수로서, 과도상태에서의 FLC출력과 정상상태에서의 PID 출력의 컨벡스(convex) 결합이다. 둘째로, 간략추론법과 개선된 컴플렉스방법을 이용한 강력한 자동동조알고리즘이 퍼지논리제어기의 성능을 자동적으로 개선하기 위하여 사용된다. 이방법은 오차변화율및 제어출력의 제한조건에 의하여, 언어제어규칙, 퍼지계수(scaling factor), PID계수, 하이브리드 퍼지논리제어기의 하중계수의 최적값을 자동적으로 추정한다. 시뮬레이션은 시간지연 플랜트및 하수처리시스템의 활성오니공정과 같은 비선형 플랜트에서 실행되고, 시스템의 성능은 평가지수 ITAE로 평가된다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4597-4603
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• 2010

A factorization is a very important part of multi-level logic synthesis. The number of literals in a factored form is an estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube nonkernel Boolean pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over previous other factorization methods.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.21-31
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• 2010

In the architectural design technologies being changed recently, there is the study to develop the way that will enable the designers to get access logically to the processes of deciding the values of design factors which depend on the experience of the designers. This study, which is one part of those studies, has been carried out to develop the model that can decide the values logically for the design factors having the character that the design values are changed by the time variation out of design factors involved in the building energy saving design. As a result, the structure of the decision model which can decide the design values logically from the computer simulation that solve the problem by interpreting the real world as the probability distribution, has been established through this study. For the application and verification of these decision model, the case study has been carried out for the outdoor climate factors that stand for the design factors having the time variation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.668-670
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• 1998

테크놀로지 매핑의 효율성은 매핑된 회로의 지연시간과 회로의 면적에 의해서 평가되어진다. 특히 순차회로에서는 레지스터 사이의 조합회로의 최대지연시간에 의해서 전체회로의 지연시간이 결정된다. 본 논문에서는 순차회로에 대한, 건설적인(Constructive) 단계와 반복적인(Iterative) 단계의 리타이밍 기술과 퍼지 논리에 의해 향상된 FPGA 매핑 알고리즘을 소개한다. 주어진 초기회로는 건설적인 방법에 의하여 FPGA회로로 초기매핑되어진후 반복적인 리타이밍에 의하여 매핑회로의 효율을 높이게된다. 초기회로에 주어진 여러 가지 기준들은 결정 함수(Decision Making)에 대한 퍼지 이론 법칙의 계층적인 구조에 의해 연결되어져 있다. 제안된 매퍼는 MCNC 밴치마커의 실험을 통해 지연시각과 면적에서 기존 매핑시스템의 성능을 능가함을 보여준다.

• Journal of Korea Multimedia Society
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• v.3 no.1
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• pp.77-90
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• 2000

Real-Time verification is a procedure that verifies the correctness of specification related to requirement in time as well as in logic. One serious problem encountered in the verification task is that the state space grows exponentially owing to the unboundedness of time, which is termed the state space explosion problem. In this paper, we propose a real-time verification technique checking the correctness of specification by showing that a system model described in timed automata is equivalent to the characteristic of system property specified in timed modal-mu calculus. For this, we propose a local model checking method based on the value of the formula in initial state with constructing product graph concerned to only the nodes needed for verification process. Since this method does not search for every state of system model, the state space is reduced drastically so that the proposed method can be applied effectively to real-time system verification.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.977-987
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• 1999

The current traffic signal control systems are operated depending on the pre-planned control scheme or the selected control scheme according to a period of time. The problem with these types of traffic control systems is that they can not cope with variant traffic flows appropriately. Such a problem can be difficult to solve by using binary logic. Therefore, in this 0paper, we propose a traffic signal control system which can deal wit various traffic flows quickly and effectively. The proposed controller is operated under uncertainty and in a fuzzy environment. It show the congestion of road traffic by using fuzzy logic, and it determines the length of green signal by means of a fuzzy inference engine. It modeled using petri-net to verify its validation.

• Journal of Korean Society of Transportation
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• v.28 no.6
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• pp.109-120
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• 2010

This study aims to develop mathematical models for estimating saturation flow rates at the stop line of signalized intersection due to Workzones in the vicinity, since the saturation flow rate is the most critical parameter in capacity analysis for signalized intersections. It was found by reference review that saturation flow rates are sensitively influenced by the location of Workzone, the number of lanes, cycle length and effective green time. Extensive microscopic simulation runs were also performed and compared to the those of mathematical models for model verification. Mathematical models were developed based on traffic flow theory and dualizing them by the location of workzones. And then each result produced by changing important parameter values was carefully examined and analyzed. Small but consistent differences in saturation flow rate values between mathematical models and simulations exist. However, the pattern of changes in saturation flow rates depending on each variable was similar.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.4
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• pp.10-21
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• 2001

This paper develops a logical simulation method for by dyversity of situations. Most existing systems, for example, games and infant tutoring systems lead users to virtual environment with unfolding situations, but are not designed to induce the change of the environment itself. In this paper, a logically simulated environment is created by defining situations and single events based on situation hierarchy structure. We elaborate the occurrence of events by classifying the causality. The occurrence or natural phenomena is dictated by physical laws and natural phenomena are expressed as the transition of the event based on event association. Specifically we define the source of the event for natural phenomena and we consider the existence of objects as a primary factor in event occurrence. The advantages of this approach include the reuse of events, that is, different events can be generated in the same flow with fresh conditions. This allows us to implement a more practical and logical environment. A drawback to this method is the difficulty in dividing a situation into events. The proposed method was implemented in the context of the change of season among natural phenomena.