• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.52-59
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• 2009

In this paper, the planar waveguide slotted array antenna is presented, which has the 3-layered structure of feeding networks for a high gain. Due to the ionosphere which generates 'Faraday rotation', the skew is happened between the signal radiated from an artificial satellite and the receiving antenna. This causes a polarization loss. In this paper, to remove this polarization loss, the dumbbell shaped linear polarizer using a single layer film is proposed. The gain of proposed antenna is 29.4dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.74-80
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• 2002

VLSI intergrated circuits like SOC(system on chip) often require a multi-clock design style for functional or performance reasons. The problems of the clock domain transition due to clock skew and clock ordering within a test cycle may result in wrong results. This paper describes a new BIST(Built-in Self Test) architecture for multi-clock systems. In the new scheme, a clock skew is eliminated by a multi-capture. Therfore, it is possible to perform at-speed test for both clock inter-domain and clock intra-domain.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.726-735
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• 2014

In accordance with 4K UHD(Ultra High Definition) LCD television's higher resolution and data expansion, LCD TV had to face problems such as increasing numbers of cables and tangible skews problems among cables. The V-by-One HS is a new interface technology in the path between the image processing IC and timing control (TCON) board. The variable speed from 600 Mbps to 3.75 Gbps effectively meets the requirements of various different pixel rates. In this paper, we use the V-by-One HS interface to illustrate our proposed simulation method of frequency resonance mode and PCB design approach to model the effects of signal integrity for high speed video signal using an IBIS models.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.10
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• pp.1197-1205
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• 2014

Recently signal transmission of ultra high-definition(4K-UHD) video system is transferred as uncompressed high speed data. However, this has a limit to compose the system because EMI between separate cables of high speed interface section and skew bring distortion of the video signal and jitter. In this paper we applied V-by-One HS interface technique to transfer uncompressed high speed data. We analyzed HSD(High Speed Differential) transmission line signal integrity. Also we applied RF transmission technique instead of UHD video pattern control interface PCB design. When we measured V-by-One HS video signal of designed 4K-UHD class signal generator, We found that the transmission performance has been signal standard.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.108-116
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• 2005

Synchronizations of intra${\cdot}$intermedia for the lecture presentation in distributed multimedia environments are difficult to guarantee accurate temporal relationship between media, due to the asynchronous errors such as the delay or loss of transferred data or the transmission characteristics of each media. The jitter phenomenon occurs when the network delay has the media arrival rate abnormal because the intra-media synchronization reflects the presentation rate. And the cumulative effective of jitters on a per media stream basis results in a skew. This phenomenon cause confusion to contents recognition of learners due to network delay and can not provide effective interaction of sender and receiver in the distance education. Therefore, this paper can be solution to problems due to network delay by maintaining the requirements of temporal relationship between more than one media. And this paper enables to suggest the inter-media synchronization method that is subject to be influenced by presentation rate, and to implement lecture presentation system for distance education.

• Journal of Korea Multimedia Society
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• v.8 no.4
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• pp.502-508
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• 2005

This paper proposes a dynamic hybrid patching technique that can improve the performance of VOD systems by adopting the advantages of both greedy patching and grace patching to use a VOD server's limited network-I/O bandwidth. The proposed technique uses grace patching to the requests for the videos, arrival intervals of which are smaller than the size of patching window, and uses greedy patching to the rest requests. In addition, proposed patching technique expands the latest particular patching multicast into a regular multicast for a new request. In result, the patching multicast data for the new request can be the data from the beginning to the skew point of the video and the holding time of a dispatched channel can exceedingly decrease. Simulation results confirm that the proposed technique is better than grace patching in terms of defection rate and average service latency.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.527-536
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• 2014

In this paper, the 50kW aerogenerator which is applicable to the microgrid was designed and analyzed by using commercial simulation program Maxwell 2D. Particularly, the suggested PMSG to reduce the cogging torque introduced the offset and skew concept. The suggested optimal value of offset and skew was decided by 2mm and 60 degree of electric angle. The simulation results of the PMSG when load operation condition showed the average harmonic distortion 1.3%, voltage 322.41V, current 94.95A, and iron loss 9.73W, eddy current loss 73.68W, copper loss 3.52kW. The capacity of aerogenerator calculated 61.56kW, and the suggested design process can be applied to higher capacity generator.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.2
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• pp.408-413
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• 1996

A self-diagnostic, air-damped, piezoresitive, cantilever-beam microaccelerometer has been designed, fabricated and tested for applications to automotive electronic airbag systems. A skew-symmetric proof-mass has been designed for self-diagnostic capability and zero transverse sensitivity. Two kinds of multi-step anisotropic etching processes are developed for beam thickness control and fillet-rounding formation, UV-curing paste has been used for sillicon-to-glass bounding. The resonant frequency of 2.07kHz has been measured from the fabricated devices. The sensitivity of 195 $\mu{V}$/g is obtained with a nonlinearity of 4% over $\pm$50g ranges. Flat amplitude response and frequency-proportional phase response have been obserbed, It is shown that the design and fabricaiton methods developed in the present study yield a simple, practical and effective mean for improving the performance, reliability as well as the reproducibility of the accelerometers.