• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.311-315
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• 2008

The switching fabric used to make high speed switching for packet transfer between input and output interface in recent internet environments. Without making any changes in order to remain ATM switching fabric, the existing structures should split/reassemble a packet to certain size, set aside cross-point buffer and will put loads on the system. In this paper, we proposed a new switch architecture, which has separated data memory plane and switching plane packet data will be stored on the separate memory structure and simultaneously only the part of the memory address pointers can pass the switching fabric. The small mini packets which have address pointer and basic information would be passed through the switching fabric. It is possible to achieve the remarkable switching performance than other switch fabrics with contending variable length packets.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.45-56
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• 2004

In this paper, we propose ATM switch architecture including ALL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of m cells which consist of ALL type 1. ALL type 2, ALL type 3/4 and ALL type 5 cells. We propose two switch fabric methods; One supports the ALL type 2 cell processing per input port, the other global ALL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. In this paper, the AAL Type 2 switch module which adapts the former method is designed using VHDL language and implemented in FPGA chip. The designed AAL Type 2 switch module operates at 52MHz. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.209-216
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• 2003

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10a
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• pp.171-172
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• 2007

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.1
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• pp.466-474
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• 2014

This paper presents the line contention avoidance experiments with an optical switch, which was selected based on the comparison analysis and evaluation of the various characteristics. For example, the function, structure, strengths and weaknesses of the optical switches. After considering the nonblocking, modularity, upgrade ability and optical power loss of the several kind of the switch fabrics, a switch was selected. The selected switch fabric by using wavelength converters was controlled to avoid contention of the optical lines. In this experiment shows an example of three cases. As a result of this experiment, optical signal shows a changed peek of optical power in output. By showing a peak it confirms that the contention was avoided. By analyzing of changed optical power according to the channel setting time and release time to control of the switch could be determined. If this analysis applied to the network design, economical and efficient structures can be formed.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.1283-1286
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• 2005

최근의 대용량 다중 분산 라우터 시스템은 다수의 라인 인터페이스 모듈들과 라우팅 처리 모듈, 스위칭 패브릭 모듈로 구성되어 있고, 고속의 패킷 스위칭 및 라우팅을 구현하기 위하여 일반적으로 입력 패킷을 외부로 전송하기 위한 기능과 제어 및 관리 기능을 담당하는 기능으로 분리하여 실행되고 있다. 이러한 라우터에서는 내부 모듈들의 프로세서들 사이에 정보 송수신을 위해 프로세서 간 통신(IPC : Interprocess Communication)이 이용되고 있다. 라우터의 기능 중 제어 및 관리 기능은 신속한 처리를 위하여 UDP/IP 방식의 IPC 가 사용되고 있는데, 이 UDP/IP 방식을 개선 방안을 제안하고 prototype 시스템을 구현하여 시험한 결과 라우터의 데이터 round trip 시간과 throughput 이 각각 15.1%, 4.3%의 개선되어 라우터의 성능이 향상되었다.

• Journal of the Korea Society of Computer and Information
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• v.11 no.1 s.39
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• pp.157-165
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• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.463-470
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• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.