• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.2
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• pp.107-112
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• 2013

In the paper, velocity controller of switching module and temperature controller for the high-voltage static var compensator are proposed. Because of the continuous increase in demand for electric power, transmission and distribution facilities of power plant are required. There is a bottleneck problem of transportation routes according to new construction and expansion of power transmission facilities. Therefore there are researches to maximize the utilization of existing facilities and to increase transmission capacity without new construction. The previous static var compensator detects voltage of input circuit of power, switches the SCR directly and generates switching noise. The proposed method increases switching velocity and decreases noise using switching control based on the voltage between both sides of SCR. Also the proposed method enhance the stability using realtime temperature control for heating of the system from increase of switching velocity. We experiment the velocity and temperature control of the proposed high-voltage static var compensator in the real environment and verify the performance of the proposed system by applying in the real field.

• Journal of IKEEE
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• v.16 no.2
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• pp.131-137
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• 2012

This paper is study on a new high efficiency DC-DC converter of discontinuous conduction mode (DCM) with zero voltage switching (ZVS). The converters of high efficiency are generally made that the power loss of the used semiconductor switching devices is minimized. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high. The soft switching operation and the system efficiency of the proposed DCM-ZVS converter are verified by digital simulation and experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.214-221
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• 2015

In this paper, we present robust estimation and detection algorithms for discrete-time switched linear systems whose output measurements are corrupted by noises. First, a mode estimation algorithm is proposed based on the minimum distance criterion. Then, state variables are also observed under the active mode estimate. Second, a detection algorithm is constructed to detect the mode switching of the switched system. With the boundedness of measurement noise, the proposed estimation algorithm returns the exact active mode and approximate state information of the switched system. In addition, the detection algorithm can detect the switching time within a pre-determined time interval after the actual switching occurred.

• Journal of Korea Society of Industrial Information Systems
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• v.25 no.5
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• pp.13-21
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• 2020

This paper proposes a sign reversal channel switching method in space-frequency block code for orthogonal frequency division multiplexing system. In case of sending source data on other antenna, it is necessary for the receiver to change combining method according to the channel variation. If one does not know the predefined channel switching sequence, it is not possible to decode the received data precisely. In transmit data symbols' exchanges for a channel switching, data symbols are exchanged according to a format of space-frequency block code. In this paper, we proposes a simple sign reversal method except exchanging data symbols between transmit antennas. It is shown that this method occurs another combining method for a simple encryption in the receiver.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.278-280
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• 2000

본 논문에서는 MPLS 네트워크 시뮬레이터를 이용하여 기존의 경로 복원 기법들을 시뮬레이션하고 각각의 성능을 비교 분석한다. MPLS 네트워크 시뮬레이터는 레이블 스위칭 기능 및 LDP와 CR-LDP를 지원하는 시뮬레이터이다. 시뮬레이션할 경로 복원 기법으로써 가장 많이 참조되고 있는 Haskin에 의해 제안된 기법과 Makam에 의해서 제안된 기법을 선택한다. 시뮬레이션 결과, Haskin의 기법은 노드에러 시에도 패킷의 손실은 거의 없지만 노드가 복구된 후에는 트래픽이 급격히 증가할 뿐만 아니라 순서가 맞지 않는 패킷의 양도 증가는 문제가 있다. Makam의 기법은 노드 에어 시에 패킷의 손실이 큰 단점을 가지고 있다.

• KIPE Magazine
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• v.6 no.1
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• pp.12-19
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• 2001

• KIPE Magazine
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• v.26 no.4
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• pp.64-69
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• 2021

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.470-471
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• 2018

This paper presents a design method for combinational digital logic systems using time domain based multiplexing and common multi-terminal extension decision diagrams. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.687-688
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• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.398-399
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• 2019

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.