• Review of KIISC
• /
• v.5 no.1
• /
• pp.18-24
• /
• 1995

이진수열 발생기인 시각제어 쉬프트 레지스터의 몇가지 예와 일반화된 상관 공격법을 살펴본다.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.3
• /
• pp.77-85
• /
• 2002

A Research of binary random sequence generator that uses a linear shift register had been studied since the 1970s. These generators were used in stream cipher. In general, the binary random sequence generator consists of linear shift registers that generate sequences of maximum period and a nonlinear filter function or a nonlinear combination function to generate a sequence of high linear complexity. Therefore, To generate a sequence that have long period as well as high linear complexity becomes an important factor to estimate safety of stream cipher. Usually, the maximum period of the sequence generated by a linear feedback shift register with L resistors is less than or equal to $2^L$-1. In this paper, we propose new binary random sequence generator that consist of L registers and 2 sub-characteristic polynomials. According to an initial state vector, the least period of the sequence generated by the proposed generator is equal to or ions than it of the sequence created by the general linear feedback shift register, and its linear complexity is increased too.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.3
• /
• pp.26-33
• /
• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• Journal of Korea Society of Industrial Information Systems
• /
• v.4 no.3
• /
• pp.90-94
• /
• 1999

To prevent the congruent output of the digital psuedo-random transformation from giving the same randomness, a transformation of seemingly random deterministic process, called Chaotic transformation, is introduced. Passing through a Chaotic transformation, each event(descriptor) will produce chaotic random sequences. haotic transformation is designed on the basis of deterministic chaos function and also can be realized by simple hardware like shift registers. The circuit of chaotic transformation implemented with the shift registers is presented and the chaotic behavior of suggested circuit is explained with the characteristics of saw-tooth function with the chaotic behavior.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.15 no.4
• /
• pp.7-13
• /
• 1978

This paper is concerned with the realization of sequential machines using shift-register modules as their memory elements. Other methods were to select shift-registers under the specific conditions and didn't consider the complexity of combinational circuits driving them. By using an integer valued function, all shift-registers with minimum length could be selected and an optimum assignment with lowest complexity could be obtained by comparing the number of input lines of combinational logic circuits driving them.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.9 no.2
• /
• pp.3-12
• /
• 1999

We introduce feedback registers and definitions of complexity of a register or a sequence generated by it. In the view point of cryptography the linear complexity of an ultimately periodic sequence is important because large one gives an enemy infeasible jobs. We state some results about the linear complexity of sum and product of two LFSRs.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.2
• /
• pp.261-269
• /
• 1993

多重의 非線形性을 위한 변환을 시행하여 발생되는 待號系列로서 Kasamie 待號系列, GMW 待號系列, 그리고 No-Kumar 待號系列의 構造的인 특성을 褸造的으로 가질 수 있는 褸合待號系列을 제시한다. 본 논문에서 제시된 待號系列은 간단한 變數의 변경으로 旣存 待號系列의 發生알고리듬으로 쉽게 변형될 수 있는 특성을 갖고 있다. 컴퓨터 시뮬레이션과 實驗을 통하여 褸合待號系列은 쉬프트레지스터 段數 n-0(mod 4)에서 發生週期 $2^n$-1,發生群 $2^n/2$+1을 가지며 褸雜도(linear span)의 개선효과를 기대할 수 있음을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.47-55
• /
• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.24 no.1
• /
• pp.51-58
• /
• 2014

A LFSR is commonly used for various stream cryptography applications to generate random numbers. A Leap-ahead LFSR was presented to generate a multi-bits random number per cycle. It only requires a single LFSR and it has an advantages in hardware complexity. However, it suffers from the significant reduction of maximum period of the generated random numbers. This paper presents the new segmented Leap-ahead LFSR to solve this problem. It consists of two segmented LFSRs. We prove the efficiency of the proposed segmented architecture using the precise mathematical analysis. We also demonstrate the proposed comparison results with other counterparts using Xinilx Vertex5 FPGA. The proposed architecture can increase 2.5 times of the maximum period of generated random numbers compared to the typical Leap-ahead architecture.

• Journal of the Korea Society of Computer and Information
• /
• v.15 no.1
• /
• pp.13-21
• /
• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.