• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

• Journal of KIISE:Databases
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• v.36 no.5
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• pp.374-385
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• 2009

Flash memory becomes increasingly popular as data storage for various devices because of its versatile features such as non-volatility, light weight, low power consumption, and shock resistance. Flash memory, however, has some distinct characteristics that make today's disk-based database technology unsuitable, such as no in-place update and the asymmetric speed of read and write operations. As a result, most traditional disk-based database systems may not provide the best attainable performance on flash memory. To maximize the database performance on flash memory, some approaches have been proposed where only the changes made to the database, i.e., logs, are written to another empty place that has born erased in advance. In this paper, we propose an efficient log management scheme for flash-based database systems. Unlike the previous approaches, the proposed approach stores logs in specially allocated blocks, called log blocks. By evenly distributing logs across log blocks, the proposed approach can significantly reduce the number of write and erase operations. Our performance evaluation shows that the proposed approaches can improve the overall system performance by reducing the number of write and erase operation compared to the previous ones.

• Journal of IKEEE
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• v.23 no.3
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• pp.954-961
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• 2019

This paper suggests an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The memory cell consists of symmetric 8 transistors, in which the latch storing data is controlled by a column-wise assistline. During the read, the data storage nodes are temporarily decoupled from the read path, thus eliminating the read disturbance. Additionally, the cell keeps the noise-vulnerable 'low' node close to the ground, thereby improving the dummy-read stability. In the write, the boosted wordline facilitates to change the contents of the memory bit. At 0.4 V supply, the advanced 8T cell achieves 65% higher dummy-read stability and 3.7 times better write-ability compared to the commercialized 8T cell. The proposed cell and circuit techniques have been verified in a 16-kbit SRAM array designed with an industrial 180-nm low-power CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Korean Society for Library and Information Science
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• v.55 no.4
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• pp.293-313
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• 2021

The aim of this study is to classify the structure levels and types of the reading program in the secondary school library. The object of analysis is the practice case of the reading program included in 'Occupying School Library by 1318 Bookworms' for recently 10 years. There are 375 cases. According to the analysis result, most of the reading programs have three layers made up of 'blend title- reading activities- educational activities'. And there are classified into eight types (lecture, viewing, presentation, exhibition, making sth, debating, answering a quiz, experience) of the reading activities. The type of reading program depend on how to combine to the educational activities(reading, writing, listening, watching, speaking, making). This attribute of educational activities match up with modularity, completeness itself and organizing system. Through modular process of educational activities, it's possible to design their own reading programs based on the reading activity by adding, compensating other educational activities.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.8
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• pp.239-244
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• 2015

WebCL was proposed for high complex computing in Javascript. Since WebCL-based applications are distributed and executed on an unspecified number of general clients, it is important to profile their performances on different clients. Several profilers have been introduced to support various programming languages but WebCL profiler has not been developed yet. In this paper, we present a WebCL profiler to evaluate WebCL-based applications and monitor the status of GPU on which they run. This profiler helps developers know the execution time of applications, memory read/write time, GPU statues such as its power consumption, temperature, and clock speed.

• Review of KIISC
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• v.4 no.1
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• pp.44-52
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• 1994

정보화 사회에서는 가계, 기업, 정보 등의 정보 활동의 주체들이 가진 정보자산은 데이타 베이스(이하DB)와 소프트웨어(S/W)로 대변할 수 있으며, 이중 DB는 정보화 사회의 기반시설의 하나라고 볼 수 있다. 특별히 통계DB는 각 주체들에게는 필수적인 정보를 갖고 있다. 금융자산의 정보, 국방에 관련된 병력, 장비, 군수물자등의 정보, 회계정보 뿐 아니라 인구센서스, 경제계획수립 등등의 다양한 분야에 이 통계 DB는 사용되고 있다. 이러한 통계DB는 기존의DB에서의 데이타의 저장, 관리, 추출 기능외에 통계적인 데이타의 분석기능이 요구되고 있다. 통계 처리를 위한 데이타베이스관리 시스템(DBMS, database management system)은 주로 기존의 DBMS 에 통계처리를 위한 기능을 추가하거나 통계를 위한 DB를 따로 구축하는 방법을 사용하고 있다. 따라서 일반적인 DB 보호 기술과 더불어 통계 의 환경을 이해하는 보호 기술이 요구되고 있다. 일반적으로 DB 를 보호하는 방법으로는 물리적인 보안(physical security)과 운영체계 보안(operating system security) 이 있으며, 이들과 함께 데이타 암호화(data encryption)의 방법을 사용하고 있다. DB 의 보안 방법에 관한 연구 중 George I. Davida 등에 의한 방법은 중국인의 나머지 정리(chinese remainder thorem)를 사용하는 암호화 알고리즘을 이용하여 레코드(record) 단위의 암호화를 하며, Khamis A. Omar등에 의한 방법은 읽기, 쓰기, 갱신의 3단계의 사용자 등급을 부여하여 DB 접근의 제약을 가하는 기능을 갖고 있다. 본고에서는 특히 그 중요성이 더해가고 있는 통계 의 일반적인 개념을 살펴보며, 특성 지향형 질의 모델(characteristic-specified query model)의 보호기술을 살펴본다. 특별히 본고는 통계 DB의 보호에 대한 일반적인 조사 연구로서 잘 알려진 사실들을 많은 참고 문헌과 더불어 소개하는 내용으로 통계 DB의 보호에 관한 새로운 연구 결과는 아니다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1277-1280
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• 2009

본 논문은 ITU-T 권고안 J-38 부록 B에 명시된 전송방식의 분석 및 시뮬레이션을 토대로 성능을 분석 하였으며 FPGA 구현시 야기되는 문제점을 나타내고, 해결방안을 제시하였다. 구현상의 문제점으로는 크게 두 가지로 분류되는데, 첫째로 다양한 부호화 방식과 변조방식 그리고 심볼 단위 및 비트 단위의 처리로 인해 많은 클럭수를 요구하는데 본 논문에서는 읽기/쓰기 메모리를 이용하여 필요한 클럭수를 줄였다. 둘째로는 펑쳐링 부호화된 TCM 복호기에 펑처링 패턴에 정확한 동기를 얻지 못하면 프레임 동기 심볼인 UW(Unique sync-Word)를 획득하지 못하여 모든 데이터가 에러 처리되기 때문에 본 논문에서는 펑처링 패턴과 UW 심볼의 동기를 맞추는 알고리즘을 제시하였다. 이러한 알고리즘 분석 및 구현상의 문제점 해결을 토대로 본 논문에서는 ITU-T J38 annex B의 하향 스트림 채널 부호화 시스템을 VHDL 언어를 사용하여 FPGA 칩에 직접 구현하였다.