• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.4
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• pp.581-586
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• 1998

We investigated the effect of mechanical back side damage in Czochralski grown silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductivity decay method, degree of X-ray diffuse scattering, X-ray section topography, and wet oxidation/preferential etching methods. The data indicate that the higher the mechanical damage intensity, the lower the minority carrier lifetime, and the magnitude of diffuse scattering and X-ray excess intensity increased proportionally, and it was at Grade 1:Grade 2:Grade 3=1:7:18.4 that the normalized relative quantization ratio of excess intensity in damaged wafer was calculated, which are normalized to the excess intensity from sample Grade 1.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.12 no.1
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• pp.27-34
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• 1999

We investigated the effect of mechanical back side damage in viewpoint of electrical and surface morphological characteristics in Czochralski silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductance decay technique, atomic force microscope, optical microscope, wet oxidation/preferential etching methods. The data indicate that the higher the mechanical damage degree, the lower the minority carrier lifetime, and surface roughness, damage depth and density of oxidation induced stacking fault increased proportionally.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.431-431
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• 2008

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.38-42
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• 1982

N+-P/P+solar cells were fabricated by using the polycrystalline silline wafer with the resistivity of 3-6 ohm-cm. minority carrier lifetimes, measured by Nd: YAG laser, were from 100ns up to 150ns. Conversion efficiency measured under AM 1 irradiation, were about 4%.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.46.1-46.1
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• 2010

Surface passivation of crystalline silicon(c-Si) surface with a-Si:H thin films has been investigated by using quasi-steady-state photo conductance(QSSPC) measurements. Analyzing the influence of a-Si:H film thickness, process gas ratio, deposition temperature and post annealing temperature on the passivation properties of c-Si, we optimized the passivation conditions at the substrate temperature of $200-250^{\circ}C$. Best surface passivation has been obtained by post-deposition annealing of a-Si:H film layer. Post annealing around the deposition temperature was sufficient to improve the surface passivation for silicon substrates. We obtained effective carrier lifetimes above 5.5 ms on average.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.128.1-128.1
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• 2011

In amorphous silicon and crystalline silicon(a-Si:H/c-Si) heterojuction solar cells, intrinsic hydrogenated amorphous silicon(a-Si:H) films play an important role to passivate the crystalline silicon wafer surfaces. We have studied the correlation between the surface passivation quality and nature of the Si-H bonding at the a-Si:H/c-Si interface. The samples were obtained by VHF-CVD under different deposition conditions. The passivation quality and analysis of all structures studied was performed by means of quasi steady state photoconductance(QSSPC) methods and fourier transform infrared spectrometer(FTIR) measurements respectively.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.6
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• pp.145-154
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• 2002

CMP (Chemical mechanical polishing) process was used to control the fine grinding process induced mechanical damage of Cz Silicon wafer. Characterization of mechanical damage was carried out using Nomarski microscope, magic mirror and also using angle lapping and lifetime scanner evaluation after heat treatment. Magic mirror and lifetime scanner were very useful for the residual damage pattern characterization and CMP process was effective on the reduction of fine grinding induced mechanical damage.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.99.2-99.2
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• 2012

현재 양산 중인 대부분의 결정질 실리콘 태양전지는 p-type 실리콘 기판의 전면에 인 (phosphorus) 을 확산시켜 에미터로 사용한 스크린 프린티드 태양전지 (Screen Printed Solar Cells) 이다. 위 태양전지의 단점은 p-type 기판의 광열화현상 (Light Induced Degradation) 문제와 후면 알루미늄 금속 전극으로 인한 휨 현상 등이 있다. 이러한 단점을 해결하기 위해 n-type 기판의 전면에 보론 (Boron) 을 도핑하여 에미터로 사용하고, 후면 전계 (Back Surface Field) 로 인 (Phosphorus)을 도핑한 태양전지에 대한 연구가 활발히 진행 중이다. 본 연구에서는, 튜브 전기로 (tube furnace) 를 이용해 n-type 실리콘 웨이퍼 전면에 보론 도핑을 하고 이와 마찬가지로 웨이퍼 후면에 인 도핑을 실시하였다. 그리고 전면과 후면의 패시베이션을 위해 얇게 산화막을 형성한 후 실리콘 질화막 (SiNx) 을 증착하였다. 에미터와 후면 전계 그리고 패시베이션 층의 특성을 평가하기 위해 QSSPC (Quasi-Steady-State PhotoConductance) 로 소수반송자 수명 (Minority Carrier Lifetime) 과 포화 전류 (Saturation current) 값을 측정하였다.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.217-224
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• 2011

of materials and simplification of process. Micro-blasting is one of the promising method for recycling of waste wafer due to their simple and low cost process. Therefore, in this paper, we make recycling wafer through the micro-blaster. A surface etched by micro-blaster forms particles, cracks and pyramid structure. A pyramid structure formed by micro-blaster has a advantage of reflectivity decrease. However, lifetime of minority carrier is decreased by particles and cracks. In order to solve this problems, we carried out the DRE(Damage Romove Etching). There are two ways to DRE process ; wet etching, dry etching. After the DRE process, we measured reflectivity and lifetime of minority carrier. Through these results, we confirmed that a wafer recycled can be used in solar cell.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.