• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1689-1695
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• 2008

The development of low-power wireless communication and low-cost multi-functional smart sensor has enabled the sensor network that can perceive the status information in remote distance. Sensor nodes are sending the collected data to the node in the base station through temporary communication path using the low-cost RF communication module. Sensor nodes get the energy supply from small batteries, however, they are installed in the locations that are not easy to replace batteries, in general, so it is necessary to minimize the average power consumption of the sensor nodes. It is known that the RF modules used for wireless communication are consuming 20-60% of the total power for sensor nodes. This study suggests the probability inference heuristic based non-periodic transmission to send the collected information to the base station node, when the calculated value by probability is bigger than an optional random value, adapting real-time to the variation characteristics of sensing datain order to improve the energy consumption used in the transmission of sensed data. In this transmission method suggested, transmitting is decided after evaluation of the data sensed by the probability inference heuristic algorithm and the directly sensed data, and the coefficient that is needed for its algorithm is decided through the reappearance rate of the algorithm verification data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.1-9
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• 2010

This paper describes a ultrasonic signal processing front-end IC for distance range meter and body detector. The burst shaped ultrasonic signal is generated by a self oscillator and its frequency range is about 40[kHz]-300[kHz]. The generated ultrasonic signal transmit through piezo resonator. The another piezo device transduce from received ultrasonic signal to electrical signals. This front-end IC contained low noise amplifier, band pass filter, busrt detector and time pulse generator and so on. This IC has two type of new idea for improve function and performance, which are self frequency control (SFC) and Variable Gain Control amplifier (VGC) scheme. The dimensions and number of external parts are minimized in order to get a smaller hardware size. This device has been fabricated in a O.6[um] double poly, double metal 40[V] High Voltage CMOS process.

• Clean Technology
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• v.20 no.3
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• pp.241-250
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• 2014

In this study, performance and environmental characteristics of cyclone vacuum cleaners are analyzed and product improvement methods are investigated to minimize environmental effect of the cleaners using the result. A simplified LCA method is used to analyze environmental characteristics of the cyclone vacuum cleaners. Two cyclone vacuum cleaners with similar specifications are chosen for the experiment. Typical characteristics of cyclone vacuum cleaners such as energy consumption, suction force, noise and temperature are measured and compared. Most environmental effect was caused by the energy consumption in use phase of life cycle. Some ideas are created to reduce energy consumption of the vacuum cleaners in use phase like installing baffle, and methods to extend exchange period of filter. It is analyzed how recyclability rate of vacuum cleaners could be improved to reduce the environmental effect in whole life of the vacuum cleaners.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.167-167
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• 2011

한국표준과학연구원에서는 국제표준화기구에서 제정한 국제규격(ISO, PNEUROP, DIN, JIS, AVS 등)에 기반을 둔 터보분자펌프의 특성평가시스템을 자체적으로 설계/제작 하였고, 터보분자펌프 1,000 L/s 급의 Database를 구축하였다. 이것을 토대로 특성평가시스템의 신뢰성 확인과 Feedback을 통한 시제품 개발 및 평가지원을 위해 터보분자펌프 2,500L/s 급의 Database를 구축한다. 터보분자펌프의 배기성능을 나타내는 가장 중요한 항목인 배기속도는 분자류 영역에 따라 상이한 가스($N_2$, He)를 사용하여 Throughput method와 Orifice method 두 가지 방법을 병행하여 측정한다. 측정함에 있어서 측정게이지, 유량계 및 Orifice conductance의 불확도에 의하여 배기 속도에 많은 측정오차를 포함하고 있다. 측정 오차를 줄이기 위하여 1% 이상의 안정성과 4%의 오차만을 허용하는 자전 회전자게이지(SRG)와 $10^{-3}$ mbar-L/s 영역까지의 유량 주입범위를 가지는 불확도 ${\pm}$3%의 정적형 유량시스템(CVFM)을 사용하였다. Orifice method의 경우 고진공영역으로 진입할수록 커질 수밖에 없는 배기속도 측정 불확도를 최소화하기 위해 검증된 유량을 이용한 Conductance 값을 제시하여 두 방법에서 얻은 배기속도의 불연속적인 문제를 해결한다. 본 연구에서는 2,500 L/s 급 터보분자펌프는 무거운 기체 $N_2$와 가벼운 기체 He을 사용하여 압축비의 변화와 분자류 영역에 따른 배기속도 변화를 연구하고, 2,500 L/s 급 터보분자펌프의 측정능력을 검증한다. 차후에 배기속도뿐만 아니라 소비전력, 소음, 진동, 온도 등의 특성평가의 전반적인 사항을 평가하여 터보분자펌프 2,500 L/s 급의 database를 완비해간다. 터보분자펌프 특성평가시스템을 사용한 1,000 L/s 급과 2,500 L/s 급 특성 Data를 비교, 분석하여 신뢰성 파악 및 표준화 방안을 개발하고, 고진공펌프 개발 주체와의 feedback 지원 기능의 infra를 구축한다.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.21-29
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• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.5
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• pp.617-624
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• 2014

Recently, photovoltaic inverter is received attention in photovoltaic with introduction of feed-in tariff. However, this inverter has problems such as inability to respond flexible at climate change due to its opening, and decrease of efficiency and lifetime due to its abnormal operation. To solve the problem, we desire to develop the eco-inverter which has a temperature control to respond easily on the change of temperature, and use the sealed structure not to affect the environment. In addition, we derive the optimal position of cooling system which is placed inside of inverter to minimize the power consumption, and proposed the effective measure to improve the efficient of inverter by deciding the number of cooling system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.