• 제목/요약/키워드: 소비전력 최소화

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KOCED performance evaluation in the wide field of wireless sensor network (무선센서망 내 KOCED 라우팅 프로토콜 광역분야 성능평가)

  • Kim, TaeHyeon;Park, Sea Young;Yun, Dai Yeol;Lee, Jong-Yong;Jung, Kye-Dong
    • The Journal of the Convergence on Culture Technology
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    • 제8권2호
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    • pp.379-384
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    • 2022
  • In a wireless sensor network, a large number of sensor nodes are deployed in an environment where direct access is difficult. It is difficult to supply power, such as replacing the battery or recharging it. It is very important to use the energy with the sensor node. Therefore, an important consideration to increase the lifetime of the network is to minimize the energy consumption of each sensor node. If the energy of the wireless sensor node is exhausted and discharged, it cannot function as a sensor node. Therefore, it is a method proposed in various protocols to minimize the energy consumption of nodes and maintain the network for a long time. We consider the center point and residual energy of the cluster, and the plot point and K-means (WSN suggests optimal clustering). We want to evaluate the performance of the KOCED protocol. We compare protocols to which the K-means algorithm, one of the latest machine learning methods, is applied, and present performance evaluation factors.

Adaptive Power Saving Mechanism of Low Power Wake-up Receivers against Battery Draining Attack (배터리 소모 공격에 대응하는 저전력 웨이크업 리시버의 적응형 파워 세이빙 메커니즘)

  • So-Yeon Kim;Seong-Won Yoon;Il-Gu Lee
    • Journal of the Korea Institute of Information Security & Cryptology
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    • 제34권3호
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    • pp.393-401
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    • 2024
  • Recently, the Internet of Things (IoT) has been widely used in industries and daily life that directly affect human safety, life, and assets. However, IoT devices, which need to meet low-cost, lightweight, and low-power requirements, face a significant problem of shortened battery lifetime due to battery draining attacks and interference. To solve this problem, the 802.11ba standard for the Wake-up Receiver (WuR) has emerged, this feature is playing a crucial role in minimizing energy consumption. However, the WuR protocol did not consider security mechanisms in order to reduce latency and overhead. Therefore, in this study, anAdaptive Power Saving Mechanism (APSM) is proposed for low-power WuR to counter battery draining attacks. APSM can minimize abnormally occurring power consumption by exponentially increasing power-saving time in environments prone to attacks. According to experimental results, the proposed APSM improved energy consumption efficiency by a minimum of 13.77% compared to the traditional Legacy Power Saving Mechanism (LPSM) when attack traffic ratio is 10% or more of the total traffic.

TCharge trap 층에 금속 공간층 삽입에 따른 charge trap flash 메모리 소자의 전기적인 특성

  • Lee, Dong-Nyeong;Jeong, Hyeon-Su;Kim, Tae
    • Proceedings of the Korean Vacuum Society Conference
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    • 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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    • pp.200.1-200.1
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    • 2015
  • Charge trap flash (CTF) 메모리 소자는 기존의 플로팅 게이트를 사용한 플래시 메모리 소자에 비해 쓰고 지우는 속도가 빠르고, 소비 전력이 적으며, 쓰고 지우는 동작에 의한 전계 스트레스에 잘 견뎌내는 장점을 가지고 있다. 그러나 CTF 메모리 소자에서도 메모리 셀의 크기가 작아짐에 따라 셀 사이의 간섭 효과를 무시할 수 없다. 인접 셀 간의 간섭현상은 측정 셀의 문턱전압을 예측할 수 없게 변화시켜 소자 동작의 신뢰성을 낮추고 성능을 저하시킨다. 본 논문에서는 셀 사이의 간섭을 줄이고 소자의 성능을 향상시키기 위해 charge trap 층에 금속 공간층을 삽입한 CTF메모리 소자의 전기적인 특성에 대해 연구하였다. 금속 공간층을 갖는 CTF 메모리 소자는 기존 CTF 메모리 소자의 트랩층 양 측면에 절연막과 금속 공간층을 증착시켜 게이트가 트랩층을 감싸는 구조를 갖는다. 인접 셀 사이에 발생하는 간섭 현상과 전계 분포를 분석하였다. 프로그램 동작 시CTF 메모리 소자 내에 형성되는 전계의 분포와 크기를 계산함으로 금속 공간층이 인접한 셀에서 형성된 전계를 차폐시켜 셀 간 간섭 현상을 최소화하는 것을 확인하였다. 이러한 결과는 인접 셀 간의 간섭현상을 최소화하면서 소자 동작의 신뢰성이 향상된 대용량 메모리 소자를 제작하는데 도움을 줄 수 있다.

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Dynamic Sink Relocation with Fuzzy Logic for WSN (WSN 환경에서 Fuzzy Logic을 활용한 동적 싱크 재배치 기법)

  • Lee, Tae-Ho;Kim, Min-Woo;Lee, Byung-Jun;Kim, Kyung-Tae;Youn, Hee-Yong
    • Proceedings of the Korean Society of Computer Information Conference
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    • 한국컴퓨터정보학회 2019년도 제60차 하계학술대회논문집 27권2호
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    • pp.99-100
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    • 2019
  • 무선 센서 네트워크(Wireless Sensor Network, WSN)에서의 싱크 이동은 전력 문제와 관련하여 해결해야할 중요한 문제이다. 또한 고정된 싱크를 사용하면 노드의 과도한 에너지 소비로 인해 네트워크 성능이 저하될 수 있는 문제점이 있다. 본 논문에서는 센서 노드의 클러스터가 퍼지 로직(Fuzzy Logic)을 기반으로 형성되고 싱크 재배치가 동적 2단계 메커니즘을 사용하여 결정되는 에너지 효율적인 싱크 재배치 기법을 제안한다. 본 논문에서 제안하는 기법은 싱크 재배치에 필요한 통신 오버 헤드를 최소화하고 데이터 패킷의 손실이나 지연을 최소화하여 싱크 재배치를 허용한다. 시뮬레이션 결과 제안 기법이 기존의 WSN의 대표적인 싱크 재배치 기법보다 네트워크 수명과 처리량 측면에서 우수하다는 것을 확인할 수 있었다.

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Resource Allocation Algorithm for Multiple RIS-Assisted UAV Networks (다중 UAV-RIS 네트워크를 위한 자원 할당 알고리즘)

  • Heejae Park;Laihyuk Park
    • Journal of Platform Technology
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    • 제11권1호
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    • pp.3-10
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    • 2023
  • Unmanned Aerial Vehicles (UAVs) have gained significant attention in 5G and 6G wireless networks due to their high flexibility and low hardware costs. However, UAV communication is still challenged by blockage and energy consumption issues. Reconfigurable Intelligent Surfaces (RISs) have emerged as a promising solution to these challenges, enabling improved spectral efficiency and reduced energy consumption by transmitting signals to users who cannot receive signals because of the obstacles. Many previous studies have focused on minimizing power consumption and data transmission delay through phase shift and power optimization. This paper proposes an algorithm that maximizes the sum rate by including bandwidth optimization. Simulation results demonstrate the effectiveness of the proposed algorithm.

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Clocked Low Power Rail-to-Rail Sense Amplifier for Ternary Content Addressable Memory (TCAM) Application (Ternary Content Addressable Memory를 위한 저 전력 Rail-to-Rail 감지 증폭기)

  • Ahn, Sang-Wook;Jung, Chang-Min;Lim, Chul-Seung;Lee, Soon-Young;Baeg, Sang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • 제49권2호
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    • pp.39-46
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    • 2012
  • The newly designed sense amplifier in this paper has rail-to-rail input range achieving low power consumption. Reducing static power consumption generated due to DC path to ground is key element for low power consumption in this paper. The proposed sense amplifier performs power-saving operation using negative feedback circuit that controls the current flow with the newly added PMOS input terminal. As a simulation result, the proposed sense amplifier consumed about over 50 % efficiency of the average power consumed by the typical Rail-to-Rail sense amplifier.

Communication Event-driven Power Management for Energy Efficient Wireless Sensor Network (에너지 효율적인 무선 센서 네트워크를 위한 통신 이벤트 기반의 전력 관리 방안에 관한 연구)

  • Hwang, Kwang-Il
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제32권7B호
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    • pp.411-421
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    • 2007
  • It is well known that the biggest problem of wireless sensor networks is power conservation. There have been two major approaches to efficiently use energy in wireless sensor networks. One is to use a dynamic power management scheme and the other is to use energy efficient protocols. In the former, the power manager is responsible for managing the proper power state of CPU and each I/O with respect to the events, but the power manager does not concern about the internal operation of the underlying network protocols. Thus such conventional power managers can waste unpredicted power during communication period. On the other hand, the energy efficient protocols are just focused on the power saving operation of the radio PHY. In this paper, we introduce an energy-efficient power saving mechanism that can significantly reduce unwanted power consumption of wireless sensor nodes through the communication event-driven power management. We show that our scheme improves the energy conservation in the entire network through simulations.

A Research on Low-power Buffer Management Algorithm based on Deep Q-Learning approach for IoT Networks (IoT 네트워크에서의 심층 강화학습 기반 저전력 버퍼 관리 기법에 관한 연구)

  • Song, Taewon
    • Journal of Internet of Things and Convergence
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    • 제8권4호
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    • pp.1-7
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    • 2022
  • As the number of IoT devices increases, power management of the cluster head, which acts as a gateway between the cluster and sink nodes in the IoT network, becomes crucial. Particularly when the cluster head is a mobile wireless terminal, the power consumption of the IoT network must be minimized over its lifetime. In addition, the delay of information transmission in the IoT network is one of the primary metrics for rapid information collecting in the IoT network. In this paper, we propose a low-power buffer management algorithm that takes into account the information transmission delay in an IoT network. By forwarding or skipping received packets utilizing deep Q learning employed in deep reinforcement learning methods, the suggested method is able to reduce power consumption while decreasing transmission delay level. The proposed approach is demonstrated to reduce power consumption and to improve delay relative to the existing buffer management technique used as a comparison in slotted ALOHA protocol.

A Study on the Characteristic of Power Consumption and Design of the Electrical Installations for the Inverter Controlled Elevator (인버터제어 승강기의 전력소비 특성과 전원설비 계획에 관한 연구)

  • 이기홍;성세진
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • 제15권2호
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    • pp.57-63
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    • 2001
  • This paper analysed the characteristic of Power consumption at many type of Inverter controlled Elevator. Especially, this paper proposed the standard value of full load currents. For this propose, it was classified by the passenger capacity and manufacture company. As a result, it is found that (i) the value is between -3[A] and 7[A] in case of elevator. That means the full load currents was smaller than the standard value of conventional operation type (ii) the value is between 0.5[kVA] and 3[kVA] in case of Power transformer. That means the transformer capacity was smaller than the standard value of conventional operation type. it was classified by the passenger capacity at inverter controlled elevator in apartment Also, to guarantee the operation stop of inverter controlled elevator, this paper proposed the redundancy method of electrical installations. the redundancy method is (i) 2 line service system and (ii) 2 distribution line system.

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Design of a CMOS Dual-Modulus Prescaler Using New High-Speed Low-Power TSPC D-Flip Flops (새로운 고속 저전력 TSPC D-플립플롭을 사용한 CMOS Dual-Modulus 프리스케일러 설계)

  • Oh, Kun-Chang;Lee, Jae-Kyong;Kang, Ki-Sub;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • 제9권2호
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    • pp.152-160
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    • 2005
  • A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

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