• Title/Summary/Keyword: 설계행렬

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Hybrid Transmitter Design for Massive MIMO Systems (대용량 MIMO 시스템을 위한 하이브리드 송신기 설계)

  • Seo, Bangwon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.3
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    • pp.49-55
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    • 2022
  • In the next generation mobile communication systems, hybrid massive multiple-input multiple output (MIMO) can be used to highly improve an achievable rate without increasing the number of RF chains. Recently, successive-interference-cancellation (SIC) based hybrid precoder design scheme was proposed to reduce the complexity. However, since this scheme uses simple diagonal matrix for baseband precoding, it cannot solve an interference problem between the transmitted streams. Also, there is a limitation for improving the data rate because of the use of one phase shifter for analog precoding. To solve these problems, in this paper we propose a digital precoding based on the SVD of the effective channel and an analog precoding using two phase shifters. Through simulation, we show that the proposed scheme has better achievable rate and SINR performances than the conventional one.

A Study on Design and Implementation of Scalable Angle Estimator Based on ESPRIT Algorithm (ESPRIT 알고리즘 기반 재구성 가능한 각도 추정기 설계에 관한 연구)

  • Dohyun Lee;Byunghyun Kim;Jongwha Chong;Sungjin Lee;Kyeongyuk Min
    • Journal of IKEEE
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    • v.27 no.4
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    • pp.624-629
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    • 2023
  • Estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that estimates the angle of a signal arriving at an array antenna using the shift invariance property of an array antenna. ESPRIT offers the good trade-off between performance and complexity. However, the ESPRIT algorithm still requires high-complexity operations such as covariance matrix and eigenvalue decomposition, so implementation with a hardware processor is essential to estimate the angle of arrival in real time. In addition, ESPRIT processors should have high performance. The performance is related to the number of antennas, and the number of antennas required for each application are different. Therefore, we proposed an ESPRIT processor that provides 2 to 8 variable antenna configurations to meet the performance and complexity requirements according to the applied field. The proposed ESPRIT processor was designed using the Verilog-HDL and implemented on a field programmable gate array (FPGA).

The Study on the Implementation of the X-Ray CT System Using the Cone-Beam for the 3D Dynamic Image Acquisition (3D 동영상획득을 위한 Cone-Beam 형 X-Ray CT 시스템 구현에 관한 연구)

  • Jeong, Chan-Woong;Jun, Kyu-Suk
    • The Journal of the Acoustical Society of Korea
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    • v.28 no.4
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    • pp.370-374
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    • 2009
  • In this paper, we presents a new cone beam computerized tomography (CB CT) system for the reconstruction of 3 dimensional dynamic images. The system using cone beam has less the exposure of radioactivity than fan beam, relatively. In the system, the reconstruction 3-D image is reconstructed with the radiation angle of X-ray in the image processing unit and transmitted to the monitor. And in the image processing unit, the Three Pass Shear Matrices, a kind of Rotation-based method, is applied to reconstruct 3D image because it has less transcendental functions than the one-pass shear matrix to decrease a time of calculations for the reconstruction 3-D image in the processor. The new system is able to get 3~5 3-D images a second, reconstruct the 3-D dynamic images in real time.

Floating Point Unit Design for the IEEE754-2008 (IEEE754-2008을 위한 고속 부동소수점 연산기 설계)

  • Hwang, Jin-Ha;Kim, Hyun-Pil;Park, Sang-Su;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.10
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    • pp.82-90
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    • 2011
  • Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.

An Efficient Adaptive Loop Filter Design for HEVC Encoder (HEVC 부호화기를 위한 효율적인 적응적 루프 필터 설계)

  • Shin, Seung-yong;Park, Seung-yong;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.295-298
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    • 2014
  • In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.

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The Optimal Configuration of Arch Structures Using Force Approximate Method (부재력(部材力) 근사해법(近似解法)을 이용(利用)한 아치구조물(構造物)의 형상최적화(形狀最適化)에 관한 연구(研究))

  • Lee, Gyu Won;Ro, Min Lae
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.13 no.2
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    • pp.95-109
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    • 1993
  • In this study, the optimal configuration of arch structure has been tested by a decomposition technique. The object of this study is to provide the method of optimizing the shapes of both two hinged and fixed arches. The problem of optimal configuration of arch structures includes the interaction formulas, the working stress, and the buckling stress constraints on the assumption that arch ribs can be approximated by a finite number of straight members. On the first level, buckling loads are calculated from the relation of the stiffness matrix and the geometric stiffness matrix by using Rayleigh-Ritz method, and the number of the structural analyses can be decreased by approximating member forces through sensitivity analysis using the design space approach. The objective function is formulated as the total weight of the structures, and the constraints are derived by including the working stress, the buckling stress, and the side limit. On the second level, the nodal point coordinates of the arch structures are used as design variables and the objective function has been taken as the weight function. By treating the nodal point coordinates as design variable, the problem of optimization can be reduced to unconstrained optimal design problem which is easy to solve. Numerical comparisons with results which are obtained from numerical tests for several arch structures with various shapes and constraints show that convergence rate is very fast regardless of constraint types and configuration of arch structures. And the optimal configuration or the arch structures obtained in this study is almost the identical one from other results. The total weight could be decreased by 17.7%-91.7% when an optimal configuration is accomplished.

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Modeling and Digital Predistortion Design of RF Power Amplifier Using Extended Memory Polynomial (확장된 메모리 다항식 모델을 이용한 전력 증폭기 모델링 및 디지털 사전 왜곡기 설계)

  • Lee, Young-Sup;Ku, Hyun-Chul;Kim, Jeong-Hwi;Ryoo, Kyoo-Tae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.11
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    • pp.1254-1264
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    • 2008
  • This paper suggests an extended memory polynomial model that improves accuracy in modeling memory effects of RF power amplifiers(PAs), and verifies effectiveness of the suggested method. The extended memory polynomial model includes cross-terms that are products of input terms that have different delay values to improve the limited accuracy of basic memory polynomial model that includes the diagonal terms of Volterra kernels. The complexity of the memoryless model, memory polynomial model, and the suggested model are compared. The extended memory polynomial model is represented with a matrix equation, and the Volterra kernels are extracted using least square method. In addition, the structure of digital predistorter and digital signal processing(DSP) algorithm based on the suggested model and indirect learning method are proposed to implement a digital predistortion linearization. To verify the suggested model, the predicted output of the model is compared with the measured output for a 10W GaN HEMT RF PA and 30 W LDMOS RF PA using 2.3 GHz WiBro input signal, and adjacent-channel power ratio(ACPR) performance with the proposed digital predistortion is measured. The proposed model increases model accuracy for the PAs, and improves the linearization performance by reducing ACPR.

Development of Efficient Analytical Model for a Diagrid Mega-Frame Super Tall Building (다이어그리드 메가프레임 초고층 건물을 위한 효율적인 해석모델의 개발)

  • Kim, Hyun-Su;Kang, Joo-Won
    • Journal of Korean Association for Spatial Structures
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    • v.11 no.3
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    • pp.95-103
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    • 2011
  • Among structural systems for complex-shaped tall buildings, diagrid system is widely used because of its structural efficiency and beauty of form. Recently, mega frame is favorably employed as a suitable structural system for skyscrapers because this structural system has sufficient stiffness against the lateral forces by combination of mega members which consist of many columns and girders. Diagrid mega frame system is expected to be promising structural system for future super tall buildings. However, it takes tremendous analysis times and engineer's efforts to predict the structural behavior of tall buildings applied with diagrid mega frame system because the diagrid mega frame structure has significant numbers of elements and nodes. Therefore, efficient analytical method for all buildings applied with diagrid mega frame system has been proposed in this study to reduce the efforts and time required for the analysis and design of diagrid mega frame structure. To this end, an efficient modelling technique using the characteristics of diagrid mega frame structures and an efficient analytical model using minimal DOFs by the matrix condensation method were proposed in this study. Based on the analysis of an example structure, the effectiveness and accuracy of the proposed method have been verified by the comparison between the results of the proposed method and the conventional method.

Embedded System Reliability Measurement Use Markov Chain Model (마르코프 체인 모델을 이용한 임베디드 시스템 신뢰도 측정)

  • Kawk Dong-Gyu;Cho Yong-Yoon;Park Ho-Byung;Yoo Chea-Woo
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.07b
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    • pp.433-435
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    • 2005
  • 임베디드 시스템은 다수의 디바이스를 컨트롤하여 시스템의 목적을 수행한다. 최근 임베디드 시스템의 요구사항이 증가함에 따라 하나의 임베디드 소프트웨어가 컨트롤하는 디바이스의 종류가 다양해지고 수도 증가하는 추세이다. 다수의 디바이스를 가지고 있는 임베디드 시스템에서 시스템의 신뢰도는 각 디바이스의 신뢰도에 많은 영향을 받는다. 본 논문은 임베디드 시스템의 신뢰도를 측정하기 위해서 통계적 신뢰도 측정 방법 중 한 가지인 마르코프 체인을 이용한 방법을 제안한다. 마르코프 체인은 여러 분야에서 복잡한 시스템을 단순화하여 모델링하고 과거의 변화를 토대로 미래를 예측할 수 있는 방법을 제공한다. 또한 전체 시스템의 확률을 행렬로 계측할 수 있는 방법을 가지고 있어 특정 부분의 확률이 전체 시스템의 확률에 미치는 영향을 산술적으로 계산할 수 있는 장점을 가지고 있다. 본 논문에서 제안하는 임베디드 소프트웨어 마르코프 체인은 테스트 대상 소스를 분석하여 디바이스를 컨트롤하는 루틴과 에러를 핸들링하는 루틴, 일반적인 루틴으로 나누어 각각을 상태로 정의한다. 정의한 각 상태간의 전이는 통계적으로 측정한 디바이스 신뢰도를 확률로 표현한다. 마르코프 체인을 이용하여 임베디드 시스템의 신뢰도를 측정하기 위한 시스템은 소스 분석기와 신뢰도 측정기로 나누어 설계한다. 소스 분석기는 테스트 대상이 되는 소스와 디바이스 드라이버 라이블러리 테이블을 입력으로 하고 소프트웨어의 마르코프 체인을 출력으로 한다 마르코프 체인은 행렬로 표현하고 연산하여 시스템의 신뢰도를 측정한다. 제안하는 시스템의 신뢰도 측정 방법은 부분이 가지고 있는 신뢰도가 전체 신뢰도에 미치는 영향을 산술적으로 측정할 수 있어 시스템이 요구하는 신뢰도에 접근할 수 있는 방법과 근거를 제공하는 장점이 있다.소시키는 장점을 갖는다.것으로 조사되었으며 40대 이상의 연령층은 점심비용으로 더 많은 지출을 하고 있는 것으로 나타났다. 4) 끼니별 한식에 대한 선호도는 아침식사의 경우가 가장 높았으며, 이는 40대와 50대에서 높게 나타났다. 점심 식사로 가장 선호되는 음식은 중식, 일식이었으며 저녁 식사에서 가장 선호되는 메뉴는 전 연령층에서 일식, 분식류 이었으며, 한식에 대한 선택 정도는 전 연령층에서 매우 낮게 나타났다. 5) 각 연령층에서 선호하는 한식에 대한 조사에서는 된장찌개가 전 연령층에서 가장 높은 선호도를 나타내었고, 김치는 40대 이상의 선호도가 30대보다 높게 나타났으며, 흥미롭게도 30세 이하의 선호도는 30대보다 높게 나타났다. 그 외에도 떡과 죽에 대한 선호도는 전 연령층에서 낮게 조사되었다. 장아찌류의 선호도는 전 연령대에서 낮았으며 특히 30세 이하에서 매우 낮게 조사되었다. 한식의 맛에 대한 만족도 조사에서는 연령이 올라갈수록 한식의 맛에 대한 만족도는 낮아지고 있었으나, 한식의 맛에 대한 만족도가 높을수록 양과 가격에 대한 만족도는 높은 경향을 나타내었다. 전반적으로 한식에 대한 선호도는 식사 때와 식사 목적에 따라 연령대 별로 다르게 나타나고 있으나, 선호도는 성별이나 세대에 관계없이 폭 넓은 선호도를 반영하고 있으며, 이는 대학생들을 대상으로 하는 연구 등에서도 나타난바 같다. 주 5일 근무제의 확산과 초 중 고생들의 토요일 휴무와 더불어 여행과 엔터테인먼트산업은 더욱 더 발전을 거듭하고 있으며, 외식은 여행과 여가 활동의 필수적인 요소로써 그 역할을 일조하고 있다. 이와 같은 여가시간의 증가는 독신자들에게는 좀더 많은 여유시간을 가족을 이루고 있는 가족구성원들에게는 가족과의 유대를 강화하는 휴식과 오락의 소비 트렌드를 창출시켰

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Analysis of Feature Importance of Ship's Berthing Velocity Using Classification Algorithms of Machine Learning (머신러닝 분류 알고리즘을 활용한 선박 접안속도 영향요소의 중요도 분석)

  • Lee, Hyeong-Tak;Lee, Sang-Won;Cho, Jang-Won;Cho, Ik-Soon
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.26 no.2
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    • pp.139-148
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    • 2020
  • The most important factor affecting the berthing energy generated when a ship berths is the berthing velocity. Thus, an accident may occur if the berthing velocity is extremely high. Several ship features influence the determination of the berthing velocity. However, previous studies have mostly focused on the size of the vessel. Therefore, the aim of this study is to analyze various features that influence berthing velocity and determine their respective importance. The data used in the analysis was based on the berthing velocity of a ship on a jetty in Korea. Using the collected data, machine learning classification algorithms were compared and analyzed, such as decision tree, random forest, logistic regression, and perceptron. As an algorithm evaluation method, indexes according to the confusion matrix were used. Consequently, perceptron demonstrated the best performance, and the feature importance was in the following order: DWT, jetty number, and state. Hence, when berthing a ship, the berthing velocity should be determined in consideration of various features, such as the size of the ship, position of the jetty, and loading condition of the cargo.