• Proceedings of the IEEK Conference
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• 대한전자공학회 2001년도 제14회 신호처리 합동 학술대회 논문집
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• pp.565-568
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• 2001

이 논문에서는 미디언 필터의 선형 조합을 통해 임의의 주파수 특성을 갖는 필터 구조와 그 설계 방법을 제안한다. Linear-phase FIR 저대역통과 필터의 홀수번째 필터 계수의 부호를 바꾸면 FIR 고대역 통과 필터를 얻을 수 있는데, 이것은 필터 계수의 부호가 모두 양수인 두 개의 부분 필터의 차와 같은 모양을 가진다. 이 과정을 일반화하여 비선형 필터에 적용하면 LCWM(linear combination of median filter)필터는 가중 미디언 부필터(sub-filter)의 선형 조합으로 구성된다. 이는 선형 대수학에서 어떤 공간상의 임의의 벡터가 그 공간의 기저 (basls) 벡터들의 선형 조합으로 표현된다는 사실과 유사하다. 따라서 부필터의 필터 계수를 기저 벡터로이용하여 얻어지는 기저 행렬과 필터의 주파수 특성을 조절하는 계수 벡터를 구함으로써 LCWM 필터를 설계할 수 있다. 제안된 필터 설계 방법을 이용하면 특정 주파수 특성을 가지는 FIR 필터와 유사한 특성을 갖는 비선형 필터 구조를 만들 수 있다. LCWM 필터는 고대역 통과, 저대역 통과, BP(band-pass), BS(band-stop)의 임의의 주파수 특성을 가지는 필터로 설계될 수 있음이 실험을 통해 확인되었다.

• Journal of the Institute of Electronics and Information Engineers
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• 제50권2호
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• pp.54-59
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• 2013

This letter presents a shorted-stub tapped branch-line coupler for dual-band applications. In the new design, a shorted stub is used to realize 90 phase change at two frequencies. Closed-form design equations are derived to find the characteristic impedance and electrical length of the proposed branch lines using the ABCD-matrix. To verify the design concept, a microstrip coupler operating at 0.8 and 1.85 GHz is fabricated and measured.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 한국퍼지및지능시스템학회 2006년도 춘계학술대회 학술발표 논문집 제16권 제1호
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• pp.75-78
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• 2006

본 논문에서 우리는 HIV-1 바이오 동역학모델의 퍼지 모델링 및 디지털 퍼지 제어 기법을 소개한다. 그것의 제어구조는 샘플링 점들에서 측정한 상태로부터 현재 상태를 대략적으로 예측하는 수치적 적분 구조를 사용한다. 제안된 지능형 디지털 재설계에서는 전역 상태-정합과 안정도 조건들을 동시적으로 만족하는 타당한 디지털 제어 이득들을 찾는 것이다. 우리는 보상된 블록-펄스 함수를 이용하여 새로운 전역 상태-정합 조건을 우선 제시하며 그리고 나서 안정도 조건들을 이 조건들에 추가한다. 유도된 조건들은 선형행렬 부등식으로 묘사되며, 그로인해 볼록 최적화 문제로 쉽게 해결될 수 있다. 또한, 안정도 조건으로 인한 성능 하강을 방지하기 위해 두 단계 지능형 디지털 재설계 과정이 제안된다. 첫 번째 단계에서는 전역 상태-정합만을 고려한 디지털 제어 이득을 찾는다. 두 번째 단계에서는 얻어진 디지털 제어하의 폐루프 시스템을 안정화 시키는 추가디지털 제어기를 설계한다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.9-12
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• 2003

This paper describes a step-by-step method to minimize design iterations in a process of product design change. In the design process, two components are coupled if a change of a component can require the other components change, and design iterations are generated by the coupling. The design iteration is one of main factors that increase design effort. In this study, three matrices are used to solve the design iteration of automatic transmission lever, Requirement-Engineering matrix, Engineering-Components matrix, and DSM(Design Structure Matrix). Firstly, with the DSM, the product architecture and conceptual design process are proposed from product function analysis. Secondly, with the QFD, the Requirement-Engineering matrix and Engineering-Components matrix present the relationship among customer requirements, engineering issues, and product components. Lastly, the results of the QFD analysis are used in the DSM to solve the component interactions and to provide design

• The KIPS Transactions:PartA
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• 제9A권3호
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제15권11호
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• pp.1082-1089
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• 2004

In this paper, miniaturization of an elliptic-response open-loop resonator filter and design flexibility using similarity transformation of the coupling matrix are proposed. Moreover, the filter with wider fractional bandwidth is designed by the proposed method. In order to verify the proposed method, three 4th-order elliptic-response open-loop resonator filters with a relative bandwidth of 4 % at the center frequency of 2.0 GHz are designed. One is realized with constant-width microstrip line resonator and the others are implemented with different-width microstrip line resonator. Compared with the former one, the latter have shown the size reduction of 13 % and 25 %, respectively. Since it may not be possible to implement the resonators with very narrow spacing for the required coupling coefficient filters with two different configurations representing same response characteristic through similarity transformation of the coupling matrix are proposed. From this design flexibility, a filter with a relative bandwidth of 8 % at the center frequency of 2.0 GHz is designed with realizable design parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권10호
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• pp.61-69
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• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

• Journal of the Computational Structural Engineering Institute of Korea
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• 제16권1호
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• pp.1-8
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• 2003

Topology optimization has been evolved into a very efficient conceptual design tool and has been utilized into design engineering processes. Traditional topology optimization has been using homogenization method and optimality criteria method. homogenization method provides relationship equation between structure which includes many holes and stiffness matrix in FEM. Optimality criteria method is used to update design variables while maintaining that volume fraction is uniform. Traditional topology optimization has advantage of good convergence but has disadvantage of too much convergency time. In one way to solve this problem, element removal method using the criterion of an average stress is presented. As the result of examples, it is certified that convergency time is very reduced.

• Journal of the Computational Structural Engineering Institute of Korea
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• 제12권1호
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• pp.95-102
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• 1999

본 연구에서는 중복되지 않는 고유치를 갖는 비비례 감쇠계의 고유치와 고유벡터의 민감도를 계산하는 새로운 방법을 제시하였다. 제안 방법에서는 (n+1)차의 대칭 행렬로 이루어진 대수방정식을 해석함으로써 n개의 자유도를 갖는 감쇠계의 고유치와 고유벡터의 설계변수에 대한 미분을 구한다. 제안 방법은 매우 간단하면서도 수치적 안정성이 보장되고 정확한 해를 주는 방법이다. 제안 방법의 검증을 위해 7자유도를 갖는 차량모델의 민감도해석을 예제에서 다루고 있다. 예제에서의 설계변수는 콘테이너의 질량으로 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제17권4호
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• pp.953-958
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• 2013

In this paper, an efficient hardware architecture is proposed for $32{\times}32$ inverse transform HEVC decoder. HEVC is a new image compression standard to deal with much larger image sizes compared with conventional image codecs, such as 4k, 8k images. To process huge image data effectively, it adopts various new block structures. Theses blocks consists of $4{\times}4$, $8{\times}8$, $16{\times}16$, and $32{\times}32$ block. This paper suggests an effective structures to process $32{\times}32$ inverse transform. This structure of inverse transform adopts the decomposed $16{\times}16$ matrixes of $32{\times}32$ matrix, and simplified the operations by implementing multiplying with shifters and adders. Additionally the operations frequency is downed by using multicycle paths. Also this structure can be easily adopted to a multi-size transform or a forward transform block in HEVC codec.