• Title/Summary/Keyword: 산술 시프트 레지스터

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Arithmetic Shift Register (산술 시프트 레지스터)

  • 박창수;손창우;조경연
    • Proceedings of the Korea Multimedia Society Conference
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    • 2003.05b
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    • pp.61-64
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    • 2003
  • 본 논문에서는 의사난수발생기로 사용할 수 있는 산술 시프트 레지스터(ASR. Arithmetic Shift Register)를 제안한다. 산술 시프트 레지스터는 GF(2ⁿ)상에서 0이 아닌 초기 값에 0 또는 1이 아닌 임의의 수를 곱하는 수열로 정의한다. 산술 시프트 레지스터의 주기는 2ⁿ-1로 최대 주기를 가진다. 또한 소프트웨어 및 하드웨어로 구현이 용이하다. 제안한 산술 시프트 레지스터는 종래의 선형귀환 시프트 레지스터와 같이 암호, 오류수정부호, 몬테카를로 적분, 데이터통신 둥 여러 분야에서 폭 넓게 사용될 수 있다.

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Generalization of Galois Linear Feedback Register (갈로이 선형 궤환 레지스터의 일반화)

  • Park Chang-Soo;Cho Gyeong-Yeon
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.43 no.1 s.307
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    • pp.1-8
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    • 2006
  • This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

Redesign of Stream Cipher Salsa20/8 (스트림 암호 Salsa20/8의 재설계)

  • Kim, Gil-Ho;Kim, Sung-Gi;Cho, Gyeong-Yeon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1904-1913
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    • 2014
  • Was develop 256bit output stream cipher of improving for same key reuse prohibition and integrity. The developed stream cipher used Salsa20 round function was implemented to hardware of applying a 5-stage pipeline architecture, such as WSN and DMB for real-time processing can satisfy the speed and security requirements.