• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.101-110
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• 1997

SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.165-170
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• 2022

By reducing time spent outside, a shopping system was developed for middle-aged and elderly people who mainly use neighborhood marts and neighborhood mart managers. The main functions of this app are direct shopping and online shopping, and it was developed using QR code using Zxing library on Android and Kakao Map using Kakao API. In addition, it provides information such as payment statistics and bulletin board posts that members need through recycler view and graphs in an easy-to-read manner. Through this system, members can efficiently manage by reducing fatigue when using the mart through direct purchase using QR code and delivery through map, and reducing manpower wastage as a mart manager. Also, as a mart manager, more consumers will be able to sell more items.

• Journal of the Korean Society of Marine Environment & Safety
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• v.30 no.4
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• pp.332-339
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• 2024

Safety is essential for organizations operating in high-risk environments, such as the Navy. Effective safety management requires continuous improvement and supplementation, commonly achieved through the PDCA (Plan-Do-Check-Act) cycle. Despite reinforced safety regulations and expanded education, safety accidents persist in the Navy, indicating a need to enhance the safety accident analysis and classification system. This study aims to analyze and identify the shortcomings of the current Navy safety accident classification system to establish a more effective framework. By doing so, we will be able to register the results of safety accidents, identify their root causes, and propose a 12-digit Navy safety accident classification code. This code will contribute to the development of mid- to long-term safety management policies.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.6
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• pp.484-492
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• 2016

The turbine is an important component and has a significant impact on the thermodynamic efficiency of the organic Rankine cycle. A precise preliminary design is essential to developing efficient turbines. In addition, performance analysis and structural analysis are needed to evaluate the performance and structural safety. However, there are only a few exclusive studies on the development process of the radial inflow turbines for the organic Rankine cycle (ORC). In this study, a preliminary design of the ORC radial inflow turbine was performed. Subsequently, the performance and structural analysis were also carried out. The RTDM, which was developed as an in-house code, was used in the preliminary design process. The results of the performance analysis were found to be in good agreement with target performances. Structural analysis of the designed turbine was also carried out in order to determine whether the material selection for this study is suitable for the flow conditions of the designed turbine, and it was found that the selected aluminum alloy is suitable for the designed turbine. However, the reliability of the preliminary design algorithms and numerical methods should be strictly verified by an actual experimental test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.111-114
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• 2008

This paper proposes an effective hardware scheme for gabor filter and thinning stage processing of a fingerprint identification algorithm based on minutiae with 80% cycle occupation of 32-bit RISC microprocessor. The algorithm was developed based on minutiae with bifurcation and ending point. The analysis of an algorithm source rode was performed using ARM emulator.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.453-457
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• 2006

프로그램 구현 방법에 편중되어온 기존의 AOSD 방법론이 최근에는 전체 개발 라이프사이클에서 초기 요구사항의 중요성이 강조되면서 요구사항 모델링, 분석, 설계분야에서 많은 연구가 진행되고 있다. 하지만, 요구사항 분석에서 추출된 관심사를 설계하여 구현 단계로 변환하는 과정에서 아직까지 상세화된 프로세스가 부족하다. 본 논문에서는 횡단 관심사 구현 명세 기법을 제시한다. 이 기법은 추출된 관심사를 구현 코드로 변환하기 위한 4단계의 프로세스로 구성되어 있다. 상세화된 명세 기법과 가이드라인은 AOSD에서 해결하기 어려운 설계에서 구현간의 갭을 줄여줌으로써 이해 및 유지보수성을 높여준다.

• Journal of Energy Engineering
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• v.9 no.1
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• pp.1-9
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• 2000

공정연계를 최소호하는 IGCC 시스템에 대한 개념설계를 수행하였다. 공정분석은 상용코드인 ASPEN PLUS를 이용하였다. 가스화기의 적절한 운전조건을 찾기위하여 가스화기를 경계조건으로 하는 액서지 민감도분석을 통하여 투입되는 슬러리와 산소의 조건을 결정하였다. 또한 , 생성가스 냉각시 현열을 최대한 회수학 ldn하여 , 열교환망을 통하여 급수를 에열하고 가스화플랜트의 각 부분에 공급하도록 공정을 구성하였다. 여분의 가열된 급수는 갑압증발시켜 복합사이클에서 동력을 생성시키는데 사용되어진다. 이와 같은 시스템은 , 가스터빈 -ASU-가스화플랜트의 공기에 의한 공정연계와, HRSG-가스냉각 및 정제시스템 간의 증기연계를 가능한 적게함으로써 공정의 운전성과 경제성을 최적으로 유지할 수 있다. 본 연구에서 제시하는 공정의 경우에, 열효율이 약 39%(고위발열량 기준)으로 나타났으며, 단위 기기 및 단위공정들의 최적화를 통하여 40%의 효율달성이 가능할 것이다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.146-149
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• 2015

한국정보통신기술협회(TTA)은 "HTML5 기반 스마트 TV 플랫폼(TTAK.KO-07.0111/R1)" 표준을 제정하였고, 스마트 TV 용 앱 생태계 활성화를 위해 표준기반 스마트 TV 앱 개발도구(SDK, Software Development Kit)를 개발하였다. 개발도구는 표준 기반 앱 개발의 전체 라이프사이클에 필요한 프로젝트 관리, 앱 오류검사, 애뮬레이션, 패키징 및 앱 서버 전송 기능을 자동화했다. 표준에 대한 이해도가 낮은 개발자들이 표준 기반 앱을 개발 할 수 있도록 코드 자동 완성 기능과 표준 적합성 검사 기능 및 샘플 앱 등을 제공함으로써, 개발자들이 앱 자체의 기능에 대한 설계와 분석에만 집중할 수 있도록 했다. 본 논문에서는 스마트 TV 앱 개발을 위한 개발도구의 소프트웨어 구조와 개발도구가 지원하는 각 기능에 대한 구현 내용에 대해 소개한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.3
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• pp.210-215
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• 2002

In this study, the computer program called Multi_Cycle, which simulates the steady-state performance (coefficient of performance, capacity, power consumption and etc.) of multi- airconditioning systems using R410A, was developed. In order to validate the simulation program, a series of case studies were carried out. The Multi_Cycle consists of several subroutines for simulating indoor units. outdoor unit, compressor, and expansion devices. and for estimating the thermodynamic and transport properties of the refrigerants and moist air. It would appear to be advantageous to use the Multi_Cycle for a performance analysis when considering various kinds of refrigerants and the complex operating conditions of each unit making up the multi-airconditioner cycle. Moreover, the Multi_Cycle would seem to be useful tool in optimizing a multi-airconditioning system and establishing economical and efficient operating conditions in the multi-airconditioner cycle. In the present study, the Multi_Cycle was programmed with Digital Visual Fortran for the main simulation code and Visual Basic for- the graphic user interface.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.