• Proceedings of the Korea Information Processing Society Conference
• /
• 2017.11a
• /
• pp.795-798
• /
• 2017

근래에 들어, 웨어러블 기기의 발전으로 사람의 움직임에 대한 측정이 손쉬워 지면서, 워킹, 러닝, 사이클링 등의 인간의 신체 활동 상태를 감지하여 더 효율적인 운동을 할 수 있도록 정보를 획득, 제공하려는 연구가 계속되고 있다. 본 연구에서는 웨어러블 기기중 하나인 스마트 인솔을 통해서 수집되는 가속도 정보와 압력 정보를 사용하여 운동시에 사람의 운동 자세를 감지하고 측정하는 시스템을 구현하였다. 사람이 헬스센터에서 수행하는 각각의 자세는 운동의 특성에 따라 시계열 신호의 표현 패턴이 다르게 나타나며 이 패턴을 통한 정확한 자세의 감지를 위해서 본 연구에서는 다양한 신호처리 알고리즘을 사용하였으며 이 경우 더 정확한 자세를 측정할 수 있음을 알 수 있었다. 따라서 본 연구에서는 정확한 자세의 감지를 위해 운동의 특징에 따라 알고리즘을 선택하여 시계열 정보를 처리 분석 하는 시스템을 제안하였으며 이를 통해 보다 정확하게 사람의 신체활동을 분석할 수 있었다.

• Journal of Internet of Things and Convergence
• /
• v.1 no.1
• /
• pp.33-38
• /
• 2015

Hardware are developed in various architecture. It is necessary to verifying value of variables in modules generated in each clock cycles for timing simulation. In this paper, a test vector generator in software type generates test vectors for timing simulation of 224-bit ECDSA hardware modules in developing stage. It provides test vectors with GUI format and text file format.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.05a
• /
• pp.419-422
• /
• 2008

국제적인 규제와 정부차원의 지원과 관리가 이뤄지고 있음에도 불구하고 기관 등에서는 여전히 소프트웨어자산에 대한 인식과 관리 소홀의 문제점을 안고 있다. 이는 관리해야 할 소프트웨어자산 범위의 모호함과 소프트웨어의 특성상 복사 및 설치가 쉽고 눈에 보이지 않아 관리 자체가 어렵기 때문이다. 즉 기업내 소프트웨어관리자는 구매부터 조달, 배포, 유지, 처분까지의 전체적인 소프트웨어 라이프사이클의 각 단계별로 수시로 변화되는 정보를 정확히 일치시키기가 쉽지 않다는 문제점이 있다. 따라서 이를 해결하기 위해서는 점검용 시스템 개발이 필요하며 점검용 시스템 성능향상을 위해 소프트웨어의 권리관리 정보의 표준화 및 레지스트리 정보 활용이 필요하다.

• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.522-531
• /
• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• Journal of Broadcast Engineering
• /
• v.17 no.6
• /
• pp.1091-1105
• /
• 2012

In this paper, we analyzed statistical characteristics and complexity of HEVC encoder as a leading research of acceleration, optimization and parallelization. Computational complexity of the HEVC encoder is approximately twice the compression performance compared to H.264/AVC. But, the increase of encoder complexity remains a problem to be solved in the future. Before performing the research on acceleration, optimization and parallelization to reduce high complexity of HEVC encoder, we measure the complexity each module for HEVC encoder using it's reference software HM 7.1. We also measured the predicted complexity of fast HEVC encoder software, used in real applications, using HM 7.1 applying fast encoding method. The complexity is measured in terms of the operating cycle of the encoder software under the common test sequences and conditions in the Windows PC environment. In addition, we analyze statistical characteristics of HEVC encoder software according to encoding structures and limitation using coded bitstreams.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.17-25
• /
• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2000.04a
• /
• pp.791-796
• /
• 2000

컴포넌트를 기반으로 애플리케이션을 구축하는 패러다임이 제시되면서 특히, 비즈니스 영역에 대한 개발과 기반 연구가 활발히 진행되고 있다. 최근 소프트웨어가 사용되는 영역이 복잡하고 대형화됨에 따라서, 문제영역의 분석을 통한 요구사항을 추출하는 일련의 작업이 점점 어렵게 인식되고, 컴포넌트를 개발하기 위한 모델기반의 방법론은 외부로 나타나는 인터페이스와 실제 구현되는 내부를 분리해서 설계하는 추세를 보이고 있다. 또한, 요구사항 단계에서의 문제점이 전체적인 소프트웨어 개발에 커다란 영향을 미치는 문제점들을 해결하기 위하여 좀더 체계적이고 총괄적인 접근으로 요구공학의 중요성이 강조되고 있다. 본 논문에서는 비즈니스 컴포넌트 개발을 지원하기 위해 문제 영역에서 올바른 요구사항을 체계화하고 분석할 뿐만아니라, 컴포넌트의 내부와 외부 설계, 개발을 고려한 도메인과 서비스 두 가지 관점을 포함한 요구공학 라이프사이클 정의하고자 한다. 또한, 도메인과 서비스 관점을 추출하기위해서 간략한 스펙을 제시하며 사례를 통해, 사용자가 원하는 실세계의 비즈니스 개념을 올바르게 적용하고, 분석, 설계, 개발단계에 유용한 정보로 사용되도록 한다.

• Journal of Fashion Business
• /
• v.22 no.5
• /
• pp.125-136
• /
• 2018

This study intended to develop a motorcycle safe vest that can be prepared against accidents by mounting a smart module (with built-in sensor) on the safe vest in order to emphasize safety among functional aspects of the motorcycle clothing. The research method investigated professional books, prior research, and Internet data to examine the characteristics of motorcycle wear and the theoretical examination of smart wear, and analyzed the functional characteristics of the design by reviewing smart jacket and vest design cases for motorcycles currently on the market. As a results of study an interface device sensor, which contains a sensor with IMU(Intertial Measurement Unit) and CPU(Central Processing Unit), was inserted into a motorcycle top in order to draw attention to the safety of motorcycle riders. The IMU sensor attached to the vest detected the tilting motion of the rider to either left or right side to obtain data on left or right direction, sudden stop, and so forth and displayed left or right turn signal and sudden stop sign on the backplate (back) through the LED module. As for charging the device to operate LEDs, a generator, which is designed to convert the heat energy in the exhaust into electric energy, was used to efficiently self-produce the power required to operate LEDs of the top while riding.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.1
• /
• pp.78-83
• /
• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

• Fashion & Textile Research Journal
• /
• v.17 no.5
• /
• pp.781-792
• /
• 2015

This study aims to develop a spring/fall motorcycle jacket for quick service transporter. Depending on the results of the previous research, this study produced the tested jacket which was improved in material, pattern, and design. For the tested jacket, 100% polyester fabric excellent in strength, durability and abrasion-resistance was selected as a major material, and Cordura was used as a partial material to improve the strength and abrasion-resistance of the sleeve side lines, elbow and shoulder areas. The retro-reflection material was applied partially in order to improve visibility of the jacket in the night or in a dark place. A total of 7 pockets were composed in the jacket for the sufficient storage spaces. The functional design elements such as the 2-way zipper and the placket at the center front, the action pleats at the upper part of back armholes, the pit-zip at armpit were applied. In addition, the sleeve pattern was bent with the shape of elbow curvature in time of driving and the back length of the jacket was lengthened 4cm. As a result of the appearance assessment, there was a significant difference from the existing jacket in all items but chest size, shoulder width, cuffs circumference, and jacket hemline circumference. In motion adaptability and field activity appropriateness assessments, the assessment grade for all items was found to be commonly higher than that of the existing jacket, and thus, the tested jacket was assessed to be suitable for a motorcycle jacket design for the quick service transporters.