• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.79-85
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• 2009

In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. However, the temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT current is measured, the switch codes of the TPC-CM is fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation for $20^{\circ}$C${\sim}$100$^{\circ}$C.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.230-234
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• 2002

Metal-ferroelectric-semiconductor(MFS) capacitors by using rapid thermal annealed $LiNbO_3$/Si structures were successfully fabricated and demonstrated nonvolatile memory operations of the MFS capacitors. The C-V characteristics of MFS capacitors showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3$thin film. The dielectric constant of the $LiNbO_3$film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V) curve was about 25. The gate leakage current density of MFS capacitor using a platinum electrode showed the least value of $1{\times}10^{-8}\textrm{A/cm}^2$ order at the electric field of 500 kV/cm. The minimum interface trap density around midgap was estimated to be about $10^{11}/cm^2$.eV. The typical measured remnant polarization(2Pr) value was about 1.2 $\mu\textrm{C/cm}^2$, in an applied electric field of $\pm$ 300 kv/cm. The ferroelectric capacitors showed no polarization degradation up to about $10^{10}$ switching cycles when subjected to symmetric bipolar voltage pulse in the 500 kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.388-388
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• 2010

In this study, Ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer films were directly deposited on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE = 70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000 ~ 4000 rpm for 2 ~ 30 seconds. After annealing in a vacuum ambient at 100 ~ $200^{\circ}C$ for 60 min, upper aluminum electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on highly doped Si wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the copolymer films have ferroelectric properties. The typical measured remnant polarization ($P_r$) and coercive filed ($E_c$) values were about $5.7\;{\mu}C/cm^2$ and 710 kV/em, respectively, in an applied electric field of ${\pm}$ 1.5 MV/em. The gate leakage current densities measured at room temperature was less than $7{\times}10^{-7}\; A/cm^2$ under a field of 1 MV/cm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.9-14
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• 2011

We have investigated the electrical properties of $AlO_x$ thin film device. The device has been fabricated top-bottom electrode structure and its transport properties are measured in order to study the resistance change. Electrical properties with linear voltage sweep on a electrodes are used to show the variation of resistance of $AlO_x$ thin film device. Fabricated $AlO_x$ thin film device with MIM structure is changed from a high conductive On-state to a low conductive Off-state by the external linear voltage sweep. It is found that the initial resistance of the $AlO_x$ thin film is low-resistance On state and reversible switching occurs. Consequently, we believe $AlO_x$ thin film is a promising material for a next-generation nonvolatile memory and other electrical applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.1-6
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• 2000

Recently, SrBi$_{2}$Ta$_{2}$ $O_{9}$(SBT) and Pb(Zr,Ti) $O_{3}$(PZT) were much attracted as materials of capacitor for ferroelectric random access memory(FRAM) with higher read/ write speed, lower power consumption and nonvolartility. SBT thin film has appeared as the most prominent fatigue free and low operation voltage. To highly integrate FRAM, SBT thin film has to be etched. A lot of papers have been reported over growth of SBT thin film and its characteristics. However, there are few reports about etching SBT thin film owing to difficult of etching ferroelectric materials. SBT thin film was etched in CF$_{4}$Ar plasma using magnetically enhanced inductively coupled plasma (MEICP) system. In order to investigate the chemical reaction on the etched surface of SBT thin films, X-ray Photoelecton spectrosocpy (XPS) and Secondary ion mass spectroscopy(SIMS) was performed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.5
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• pp.268-273
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• 2016

In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The $WO_x$ material was used between metal electrodes as the oxide insulator. The structure of the $Al/WO_x/TiN$ shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at -2.6V. The reset process from LRS to HRS occurred at 2.78V. The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable $V_{set}$ and $V_{reset}$ were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm's Law ${\rightarrow}$ Trap-Controlled Space Charge Limited Current ${\rightarrow}$ Ohm's Law) process in the positive voltage region.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.127-127
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• 2011

전하 트랩형 비휘발성 메모리는 10년 이상의 데이터 보존 능력과 빠른 쓰기/지우기 속도가 요구 된다. 그러나 두 가지 특성은 터널 산화막의 두께에 따라 서로 trade off 관계를 갖는다. 즉, 두 가지 특성을 모두 만족 시키면서 scaling down 하기는 매우 힘들다. 이것의 해결책으로 적층된 유전막을 터널 산화막으로 사용하여 쓰기/지우기 속도와 데이터 보존 특성을 만족하는 Tunnel Barrier engineered Memory (TBM)이 있다. TBM은 가운데 장벽은 높고 기판과 전극쪽의 장벽이 낮은 crested barrier type이 있으며, 이와 반대로 가운데 장벽은 낮고 기판과 전극쪽의 장벽이 높은 VARIOT barrier type이 있다. 일반적으로 유전율과 밴드갭(band gap)의 관계는 유전율이 클수록 밴드갭이 작은 특성을 갖는다. 이러한 관계로 인해 일반적으로 crested type의 터널 산화막층은 high-k/low-k/high-k의 물질로 적층되며, VARIOT type은 low-k/high-k/low-k의 물질로 적층된다. 이 형태는 밴드갭이 다른 물질을 적층했을 때 전계에 따라 터널 장벽의 변화가 민감하여 전자의 장벽 투과율이 매우 빠르게 변화하는 특징을 갖는다. 결국 전계에 민감도 향상으로 쓰기/지우기 속도가 향상되며 적층된 유전막의 물리적 두께의 증가로 인해 데이터 보존 특성 또한 향상되는 장점을 갖는다. 본 연구에서는 SiO2/Al2O3 (2/3 nm)와 SiO2/HfAlO (2/3 nm)의 이중 터널 산화막을 증착 시킨 MIS capacitor를 제작한 후 터널 산화막에 전하가 트랩되는 것을 피하기 위하여 다양한 열처리 온도에 따른 current-voltage (I-V), capacitance-voltage (C-V), constant current stress (CCS) 특성을 평가하였다. 급속열처리 공정온도는 600, 700, 800, 900 ${^{\circ}C}$에서 진행하였으며, 낮은 누설전류, 터널링 전류의 증가, 전하의 트랩현상이 최소화되는 열처리 공정의 최적화 실험을 진행하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.6
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• pp.297-301
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• 2006

In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.39-45
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• 1998

SrBi$_{2}$Ta$_{2}$O$_{9}$ (SBT) ferroelectric thin films for nonvolatile memory were prepared on Pt/Ti/SiO$_{2}$/Si and RuO$_{2}$/SiO$_{2}$/Si substrates by RF magnetron sputtering. The dependences of crystalline and electrical properties on the lower electrode type(Pt and RuO$_{2}$) and the annealing temperatures were investigated. SBT films regardless of their electrode types showed typeical Bi layered peroviskite crystal structures. The crystalline quality of as-deposited SBT films was improved by the rapid thermal annealing at 650.deg. C for 30 sec. The remanetn polarization of 2Pr (Pr+-Pr-) of the annealed SBT films deposited on Pt/Ti/SiO$_{2}$/Si substrates were about 11 .mu.C/cm$^{2}$ and 3 .mu.C/cm$^{2}$, respectively. The leakage currents at 3 V bias voltage were about 0.8 .mu.A/cm$^{2}$ for SBT/ Pt/Ti/SiO$_{2}$/Si and about 1 .mu.A/cm$^{2}$ for SBT/RuO$_{2}$/SiO$_{2}$/Si sample. SBT films annealed at 650 .deg. C showed no degradation in Pr values after 10$^{11}$ polarization switching cycles, indicating good fatigue properties. In addition, for SBT samples deposited on Pt/Ti/SiO$_{2}$/Si, Pr values increased to more than that of initial state, suggesting the increament of leakage current caused by repeated polarization.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.5
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• pp.386-389
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• 2009

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.