• Korean Journal of Materials Research
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• v.10 no.3
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• pp.199-203
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• 2000

$Ta_2_O5$ and $Sr_0.8Bi_2.4Ta_2O_9$ films were deposited on p-type Si(100) substrates by a rf-magnetron sputtering and the metal organic decomposition (MOD), respectively.The electrical characteristics of the $Pt/SBT/Ta_2O_5/Si$ structure were obtained as the functions of $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering and $Ta_2_O5$ thickness. And to certify the role of $Ta_2_O5$ as a buffer layer, the electrical characteristics of $Pt/SBT/Ta_2O_5/Si$ were compared. $Pt/SBT/Ta_2O_5/Si$ capacitor with 20% $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering did now show typical C-V curve of metal/ferroelectric/insulator/semiconductor (MFIS) structure. The capacitor with 20% $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering had the largest memory window. And the memory window was decreased as the $Ta_2_O5$ gas flow ratio during the $Ta_2_O5$ sputtering was increased to 40%, 60%. In the C-V characteristics of the $Pt/SBT/Ta_2O_5/Si$ capacitors with the different $Ta_2_O5$ thickness, the capacitor with 26nm thickness of $Ta_2_O5$ had the largest memory window. The C-V and leakage current characteristics of the Pt/SBT/Si structure were worse than those of $Pt/SBT/Ta_2O_5/Si$ structure. These results and Auger electron spectroscopy (AES) measurement showed that $Ta_2_O5$ films as a buffer layer tool a role to prevent from the formation of intermediate phase and interdiffusion between SBT and Si.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.171-180
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• 2009

Slowly, but surely, we are seeing the emergence of a variety of embedded systems that are employing Storage Class RAM (SCRAM) such as FeRAM, MRAM and PRAM, SCRAM not only has DRAM-characteristic, that is, random byte-unit access capability, but also Disk-characteristic, that is, non-volatility. In this paper, we propose a new software architecture that allows SCRAM to be used both for main memory and for secondary storage simultaneously- The proposed software architecture has two core modules, one is a SCRAM driver and the other is a SCRAM manager. The SCRAM driver takes care of SCRAM directly and exports low level interfaces required for upper layer software modules including traditional file systems, buddy systems and our SCRAM manager. The SCRAM manager treats file objects and memory objects as a single object and deals with them in a unified way so that they can be interchanged without copy overheads. Experiments conducted on real embedded board with FeRAM have shown that the SCRAM driver indeed supports both the traditional F AT file system and buddy system seamlessly. The results also have revealed that the SCRAM manager makes effective use of both characteristics of SCRAM and performs an order of magnitude better than the traditional file system and buddy system.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.236.2-236.2
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• 2014

세계 반도체 시장은 컴퓨터 기능이 더해진 모바일 기기의 수요가 증가함에 따라 메모리반도체의 시장규모가 최근 빠른 속도로 증가했다. 특히 모바일 기기에서 저장장치 역할을 하는 비휘발성 반도체인 NAND Flash Memory는 스마트폰 및 태블릿PC 등 휴대용 기기의 수요 증가, SSD (Solid State Drive)를 탑재한 PC의 수요 확대, 서버용 SSD시장의 활성화 등으로 연평균 18.9%의 성장을 보이고 있다. 이러한 경제적인 배경 속에서 NAND Flash 미세공정 기술의 마지막 단계로 여겨지는 1Xnm 공정이 개발되었다. 그러나 1Xnm Flash Memory의 생산은 새로운 제조설비 구축과 차세대 공정 기술의 적용으로 제조비용이 상승하는 단점이 있다. 이에 따라 제조공정기술을 미세화하지 않고 기존의 수평적 셀구조에서 수직적 셀구조로 설계 구조를 다양화하는 기술이 대두되고 있는데 이 중 Flash Memory의 대용량화와 수명 향상을 동시에 추구할 수 있는 3D NAND 기술이 주목을 받게 되면서 공정기술의 변화도 함께 대두되고 있다. 3D NAND 기술은 기존라인에서 전환하는데 드는 비용이 크지 않으며, 노광장비의 중요도가 축소되는 반면, 증착(Chemical Vapor Deposition) 및 식각공정(Etching)의 기술적 난이도와 스텝수가 증가한다. 이 중 V-NAND 3D 기술에서 사용하는 박막증착 공정의 경우 산화막과 질화막을 번갈아 증착하여 30layer 이상을 하나의 챔버 내에서 연속으로 증착한다. 다층막 증착 공정이 비정상적으로 진행되었을 경우, V-NAND Flash Memory를 제조하기 위한 후속공정에 영향을 미쳐 웨이퍼를 폐기해야 하는 손실을 초래할 수 있다. 본 연구에서는 V-NAND 다층막 증착공정 중에 다층막의 두께를 가상 계측하는 알고리즘을 개발하고자 하였다. 증착공정이 진행될수록 박막의 두께는 증가하여 커패시터 관점에서 변화가 생겨 RF 신호의 진폭과 위상의 변화가 생긴다는 점을 착안하여 증착 공정 중 PECVD 장비 RF matcher와 heater에서 RF 신호의 진폭과 위상을 실시간으로 측정하여 데이터를 수집하고, 박막의 두께와의 상관성을 분석하였다. 이 연구 결과를 토대로 V-NAND Flash memory 제조 품질향상 및 웨이퍼 손실 최소화를 실현하여 제조 시스템을 효율적으로 운영할 수 있는 효과를 기대할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.5
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• pp.975-981
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• 2017

In this paper, we propose a method for efficient use of energy when using flash device in WSN environment. Typical Flash devices have a drawback to be an energy efficient storage media in the energy-constrained WSNs due to the high standby energy. An energy efficient approach to deploy Flash devices into WSNs is simply turning the Flash device off whenever idle. In this regard, we make the simple but ideal approach realistic by removing these two obstacles by exploiting nonvolatile RAM (NVRAM), which is an emerging memory technology that provides both non-volatility and byte-addressability. Specifically, we make use of NVRAM as an extension of metadata storage to remove the FTL metadata scanning process that mainly incurs the two obstacles. Through the implementation and evaluation in a real system environment, we verify that significant energy savings without sacrificing I/O performance are feasible in WSNs by turning off the Flash device exploiting NVRAM whenever it becomes idle. Experimental results show that the proposed method consumes only about 1.087% energy compared to the conventional storage device.

• Journal of KIISE
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• v.42 no.4
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• pp.427-433
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• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

• KIPS Transactions on Software and Data Engineering
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• v.12 no.3
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• pp.111-116
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• 2023

The WiscKey database, which optimizes overhead by compaction of the LSM tree-based Key-Value database, stores the value in a separate file, and stores only the key and value addresses in the database. Each time an fsync system call function is used to ensure data integrity in the process of storing values. In previously conducted studies, workload performance was reduced by up to 5.8 times as a result of performing the workload without calling the fsync system call function. However, it is difficult to ensure the data integrity of the database without using the fsync system call function. In this paper, to reduce the overhead of the fsync system call function while performing workloads on the WiscKey database, we use NVDIMM caching techniques to ensure data integrity while improving the performance of the WiscKey database.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.27-32
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• 1999

Metal-ferroelectric-semiconductor devices by susing rapid thermal annealed $LiNbO_3/Si$(100) structures were fabricated and demonstrated nonvolatile memory operations. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were about $600cm^2/V{\cdot}s$ and 0.16mS/mm, respectively. The ID-VG characteristics of MFSFET's showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3 films. The drain current of the on state was more than 4 orders of magnitude larger than the off state current at the same read gate voltage of 0.5V, which means the memory operation of the MFSFET. A write voltage as low as ${\pm}3V$, which is applicable to low power integrated circuits, was used for polarization reversal. The ferroelectric capacitors showed no polarization degradation up to $10^{10}$ switching cycles with the application of symmetric bipolar voltage pulse (peak-to-peak 6V, 50% duty cycle) of 500kHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.255-255
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• 2016

Resistive random access memory (ReRAM)는 낮은 동작 전압, 빠른 동작 속도, 고집적화 등의 장점으로 인해 차세대 비휘발성 메모리 소자로써 많은 관심을 받고 있다. 최근에 ReRAM 절연막으로 NiOx, TiOx, AlOx TaOx, HfOx와 같은 binary metal oxide 물질들을 적용하는 연구가 활발히 진행되고 있다. 특히, HfOx는 안정적인 동작 특성을 나타낸다는 점에서 ReRAM 절연막 물질로 적합하다고 보고되고 있다. ReRAM 절연막을 형성할 때, 물리 기상 증착 방법 (PVD)이나 화학 기상 증착법 (CVD)과 같은 방법이 많이 이용된다. 이러한 증착 방법들은 고품질의 박막을 형성시킬 수 있는 장점이 있다. 하지만, 높은 온도에서의 공정과 고가의 진공 장비가 이용되기 때문에 경제적인 문제가 있으며, 기판 또는 금속에 플라즈마 손상으로 인한 문제가 발생할 수 있다. 따라서 이러한 문제점들을 개선하기 위해 용액 공정이 많은 관심을 받고 있다. 용액 공정은 공정과정이 간단할 뿐만 아니라 소자의 대면적화가 가능하고 공정온도가 낮으며 고가의 진공장비가 필요하지 않은 장점을 가진다. 따라서 본 연구에서는, 용액공정을 이용하여 HfOx 기반의 ReRAM 제작하였고 $25^{\circ}C$와 $85^{\circ}C$에서 ReRAM의 동작특성에 미치는 compliance current의 영향을 평가하였다. 실험 방법으로는, hafnium chloride (0.1 M)를 2-methoxyethanol에 충분히 용해시켜서 precursor를 제작하였다. 이후, p-type Si 기판 위에 습식산화를 통하여 300 nm 두께의 SiO2 절연층을 성장시킨 후, 하부전극을 형성하기 위해 electron beam evaporation을 이용하여 10/100 nm 두께의 Ti/Pt 전극을 증착하였다. 순차적으로, 제작된 산화물 precursor를 이용하여 Pt 위에 spin coating 방법으로 1000 rpm 10 초, 6000 rpm 30초의 조건으로 두께 35 nm의 HfOx 막을 증착하였다. 최종적으로, solvent 및 불순물을 제거하기 위해 $180^{\circ}C$의 온도에서 10 분 동안 열처리를 진행하였으며, 상부 전극을 형성하기 위해 electron beam evaporation을 이용하여 Ti와 Al을 각각 50 nm, 100 nm의 두께로 증착하였다. ReRAM 동작에서 compliance current가 미치는 영향을 평가하기 위하여 compliance current를 10mA에서 1mA까지 변화시키면서 측정한 결과, $25^{\circ}C$에서는 compliance current의 크기와 상관없이 일정한 메모리 윈도우와 우수한 endurance 특성을 얻는 것을 확인하였다. 한편, $85^{\circ}C$의 고온에서 측정한 경우에는 1mA의 compliance current를 적용하였을 때, $25^{\circ}C$에서 측정된 메모리 윈도우 크기를 비슷하게 유지하면서 더 우수한 endurance 특성을 얻는 것을 확인하였다. 결과적으로, 용액공정 방법으로 제작된 ReRAM을 측정하는데 있어서 compliance current를 줄이면 보다 우수한 endurance 특성을 얻을 수 있으며, ReRAM 소자의 전력소비감소에 효과적이라고 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1858-1864
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• 2009

In this paper, we design a non-volatile memory IP, 1-kb one-time programmable (OTP) memory, used for power management ICs. Since a conventional OTP cell uses an isolated NMOS transistor as an antifuse, there is an advantage of it big cell size with the BCD process. We use, therefore, a PMOS transistor as an antifuse in lieu of the isolated NMOS transistor and minimize the cell size by optimizing the size of a OTP cell transistor. And we add an ESD protection circuit to the OTP core circuit to prevent an arbitrary cell from being programmed by a high voltage between the terminals of the PMOS antifuse when the ESD test is done. Furthermore, we propose a method of turning on a PMOS pull-up transistor of high impedance to eliminate a gate coupling noise in reading a non-programmed cell. The layout size of the designed 1-kb PMOS-type antifuse OTP IP with Dongbu's $0.18{\mu}m$ BCD is $129.93{\times}452.26{\mu}m^2$.