• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1501-1509
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• 2001

Recently, the use of wireless communication systems has been rapidly increasing, which results in a difficult problem in efficient control of limited frequency resources. As a way of solving this problem, the ultra wideband time hopping impulse radio system attracts much attention. The impulse radio system communicates pulse position modulated data using Gaussian monocycle pulses of very short duration less than 1 nsec. Thus the transmitted signal has very low power spectral density and ultra wide bandwidth from near D.C. to a few GHz. It is blown that it hardly interferes with the existing communication systems because of its very low power spectral density. The purpose of this paper is to characterize multipath propagation of the impulse radio signal and to evaluate the performance of the correlator-based receiver for the multipath environments. In this paper, we consider the deterministic two-path model and the statistical indoor multipath model of Saleh and Valenzuela. For the two-path model the output of the correlator with the ideal reference waveform varies according to the relative difference between the indirect path delay and the time interval of PPM, and to the indirect path gains. In addition, the characteristics of bit error rates is measured for the two models through computer simulation. The simulation results indicate that the performance of the impulse radio system depends both on the relative difference between the indirect path delay and the time interval of PPM, and on the indirect path gains. Furthermore, it is observed that the reference signal designed for the AWGN channel can not be applied to the multipath channels.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.6
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• pp.4125-4130
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• 2015

This paper presents the communication performance for the radiation pattern reconfigurable antenna in the wearable device measuring bio signal (temperature, blood pressure, pulse etc.) of human body. The operational frequency is 2.4 - 2.5 GHz, which covers Bluetooth communication bandwidth. The maximum gain of the antennas is 1.96 dBi. The proposed antenna is efficiently transmitting and receiving signal by generating two opposite beam directions using two RF switches (PIN diode). Also, we investigated how radiation pattern changes according to three angles ($30^{\circ}$, $90^{\circ}$, $150^{\circ}$) of Top Loading. In this paper, we measured and compared the SNR (Signal-to-Noise Ratio) and BER (Bit Error Rate) performances of the proposed antennas in the condition between an ideal environment of anechoic chamber and smart house existing practical electromagnetic interferences (Universal Software Radio Peripheral, USRP). Throughout the comparing the results of the measurement of two cases, we found that the SNR is degraded over 5dB in average and BER is increased over ten times in maximum, therefore, it is confirmed that the error rate of receiving signal is increased. The measured results of SNR and BER value in this paper able to expect the performance degrading by the interference from the electromagnetic devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.295-298
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• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.11
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• pp.801-807
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• 2022

In this paper, we propose an ultra compact S-Band PCM/FM telemetry transmitter. The equipment is compact, so it can be applied to a limited space and capable of stable data transmission was designed and manufactured even with specifications set differently for each operating environment and system. RF direct conversion structure is used for the miniaturization of equipment, an RF transmission board, Power distribution board, and a signal processing board were implemented on a single PCB, so that the function of the transmitter could be performed with a minimum device. According to the target specification, variable output of 1~10W and variable data rate of 390kbps~12.5Mbps is possible in S-Band(2,200~2,400MHz) without degradation of performance. To verify the performance of the equipment, the RF performance test and BER measurement test were performed after the equipment was manufactured. It was confirmed that the OBW, null-to-null bandwidth, 1st IMD, Spurious emission, Phase noise specification of the PCM/FM modulated signal which is presented by the IRIG standard were satisfied, and we can confirm the data received using the transmitter inspection equipment were transmitted normally without distortion.