• Title/Summary/Keyword: 비트 주파수

Search Result 637, Processing Time 0.025 seconds

Performance of Hybrid DS/FH Spread-Spectrum Systems in Cellular Packet Radio Network (셀룰러 패킷무선망에서 하이브리드 DS/FH 확산대역 시스팀의 성능)

  • 조현욱;박상규
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.24 no.10A
    • /
    • pp.1462-1470
    • /
    • 1999
  • In this paper, the performance of packet radio networks using the ALOHA protocol in Rayleigh fading channels is analyzed in terms of the capture probability and the throughput. We consider capture effect in order to increase the probability of the channel access and to include cellular environment we assume that the traffic is a truncated bell-shaped distribution. The packet proposed in this paper consists of a competition part and a data part to decrease the probability of collision in the channel access. In the competition part, DS system with common spreading code is used and in the data, hybrid DS/FH system is used. We consider the linear correlation receiver and the hard-limiting correlation receiver as the receiver model. BPSK modulation is also employed. Because hybrid DS/FH systems are not sensitive to variation of the interference power, as we choose a proper chip number N and a frequency hopping number q, we can obtain a steady system performance even though the variation of interference power is severe fading channels such as Rayleigh fading.

  • PDF

A BER Analysis of a Space-Time Signal Processing Scheme that Combines Transmitter Diversity and Beamforming in Correlated Fading (상관 페이딩에서의 송신 다이버시티와 송신 빔형성 기술을 결합한 시공간 신호 처리 구조의 BER 해석)

  • 김일한;전주환
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.29 no.2C
    • /
    • pp.247-254
    • /
    • 2004
  • We introduce a new space-time signal processing scheme that uses both transmitter diversity technique and transmitter beamforming technique for code-division multiple access (CDMA) systems. Over complex Gaussian Rayleigh channel, the introduced scheme achieves the diveristy gain through the transmitter diversity technique. and the SNR gain by th transmitter beamforming technique. Bit error rate (BER) analyses are given to each of the three cases in which the transmitter diversity scheme, the transmitter beamforming scheme and the introduced scheme are used, in the slowly varying Rayleigh frequency nonselective fading channel. The Monte-Carlo simulation results are shown to match to the analytic results. When the channels between distant antennas are independent, analytic results show that the introduced scheme achieves the lowest $E_{b/}$ $N_{0}$ at target BER 10$^{-6}$ . When the channels between distant antennas are correlated, analytic and simulation results show that the introduced scheme is more robust to the change of channel correlation.n.

Adaptive Dual-Hop Transmission Based On Hierarchical Modulation in UWB System (초광대역 시스템의 계층변조 기반 적응적 듀얼 홉 전송 기법)

  • Kim, Dae-Hwan;Song, Hyoung-Kyu;Cho, We-Duke
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.36 no.7C
    • /
    • pp.443-450
    • /
    • 2011
  • Recently, various transmission techniques for communication and broadcasting systems have been developed to meet the dramatically increasing requirement of consumers. Because UWB (Ultra-Wideband) is a wireless communication technique that supports high data rate with low power, it can satisfy the requirement and can be applied to various wireless communication services. The multi-band orthogonal frequency division multiplexing (MB-OFDM) system, one of UWB system, is the wireless communication system that satisfies the transmission characteristic for UWB and so it can be used for various wireless communication services. In this paper, we propose a scheme that uses hierarchical modulation which is applied in digital video broadcasting system at the source and adaptive modulation based on the channel quality at the relays. The simulation results have shown that the proposed scheme has both the advantages of the increased throughput by 33% and similar BER performance to conventional scheme.

A New Selected Mapping Scheme without Side Information Using Cross-Correlation (상호 상관을 이용한 부가정보가 필요 없는 Selected Mapping 수신방법 제안)

  • Lee, Jong-keun;Chang, Dae-ig
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.42 no.4
    • /
    • pp.739-746
    • /
    • 2017
  • Orthogonal frequency division multiplexing(OFDM) systems have many advantages. However, OFDM systems are much affected by a nonlinear distortion because those systems have a high peak to average power ratio(PAPR) value. A selected mapping technology was suggested to reduce a PAPR value. The technology does not have data loss but receivers need side information to know modified phase sequence. Therefore, side information causes decreased a transmission efficiency. In this paper, we suggest a blind SLM receiver using a cross correlation technology. This receiver does not require side information. The proposed blind SLM receiver calculates sums of cross-correlation between transmitted pilot signals multiplied by each phase sequence and received pilot signals. So, this receiver detects side information which has a maximum sum cross-correlation value. We compared our proposed SLM receiver to a conventional blind SLM receiver through bit error rate(BER) and side information error rate(SIER) performances. Simulation results show that the proposed SLM receiver has improved BER and SIER performances than the conventional SLM receiver.

A Study on the 4-bit Microwave Phase Shiftter with PIN Diode (PIN 다이오드를 이용한 초고주파 4-비트 위상기에 관한 연구)

  • Cho, Young-Song;Kweon, Heag-Joong;Lee, Young-Chul;Shin, Chull-Chai
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.27 no.2
    • /
    • pp.47-54
    • /
    • 1990
  • In this paper, we design the 4-bit phase shifter which have $22.5^{\circ},45^{\circ},90^{\circ}$ and $180^{\circ}$ phase shift by applying the loaded line and switched network phase shifter. Its phase shift is variable with changing of the stub and passive device parameters. The experiments show the 6.5 dB average insertion loss and $10^{\circ}$ average phase error at center frequency, 6GHz. The results of experiment agree well with the theories except $180^{\circ}$ phase shifter.

  • PDF

Study on Integrated for Capacitive Pressure Sensor (용량성 압력센서의 집적화에 관한 연구)

  • 이윤희
    • Journal of the Korean Institute of Telematics and Electronics T
    • /
    • v.35T no.1
    • /
    • pp.48-58
    • /
    • 1998
  • For the purpose of designing novel capacitance pressure sensor, several effects on sensitivity such as parasitic capacitance effects, temperature/thermal drift and leakage current have to be eleiminated. This paper proposed the experimental studies on frequency compensation method by electronic circuit technique, C-V converting method with switched capacitor and C-F converting method with schmitt trigger circuit. The third interface circuit by frequency compensation method is composed to eliminate the drift and leakage component by comparision sensing frequency with reference frequency. The signal transmission is realized by digital signal to minimize the influence of noise and high resolution is obtained by means of increasing the number of digital bits. In the fabricated high performance C-V interface, the offset voltage was not appeared, and in case of voltage source, 4.0V, feed back capacitance, 10㎊, the pressure, 0~10 ㎪, the sensitivity of C-V converter is 28 ㎷/㎪.V, the temperature drift characteristic, 0.051 %F.S./$^{\circ}C$ and C-F converter shows -6.6 Hz/pa, 0.078 %F.S./$^{\circ}C$ respectively, relatively good ones.

  • PDF

Design of Asynchronous Library and Implementation of Interface for Heterogeneous System (비동기 라이브러리 설계와 Heterogeneous시스템을 위한 인테페이스 설계)

  • Jung, Hwi-Sung;Lee, Joon-Il;Lee, Moon-Key
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.37 no.9
    • /
    • pp.47-54
    • /
    • 2000
  • We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

  • PDF

An Efficient Mode Selection Method for OFDM Based Multi-System Wireless Communication Systems (OFDM 기반 다중 무선 통신 환경에서의 효과적인 모드 선택 기법)

  • Park, Jong-Min;Kang, Min-Soo;Cho, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.45 no.2
    • /
    • pp.19-25
    • /
    • 2008
  • When there are numerous wireless communication systems co-existing in the limited available frequency resource, an unexpected time delay can be caused during the system switching. So, in order to reduce this time delay, a mode selection method is required. In this paper, we propose a mode selection method to minimize the time delay for multi-system wireless communication systems. For the sake of efficiency, the mode selection method is designed by analyzing the preamble characteristics of different standards. Instead of performing a full search, we propose the preamble partial search to reduce the time delay to a minimum. Simulated with Matlab in an additive white Gaussian noise(AWGN) environment with a signal to noise ratio(SNR) of 10dB and bit error rate(BER) of $10^{-6}$, we evaluated and showed the performance improvement gained by using our proposed mode selection method.

Parallel Architecture Design of H.264/AVC CAVLC for UD Video Realtime Processing (UD(Ultra Definition) 동영상 실시간 처리를 위한 H.264/AVC CAVLC 병렬 아키텍처 설계)

  • Ko, Byung Soo;Kong, Jin-Hyeung
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.50 no.5
    • /
    • pp.112-120
    • /
    • 2013
  • In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

Second-order Sigma-Delta Modulator for Mobile BMIC Applications (모바일 기기용 BMIC를 위한 2차 시그마 델타 모듈레이터)

  • Park, Chulkyu;Jang, Kichang;Kim, Hyojae;Choi, Joongho
    • Journal of IKEEE
    • /
    • v.18 no.2
    • /
    • pp.263-271
    • /
    • 2014
  • This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.