• Title/Summary/Keyword: 비트 주파수

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FPGA Implementation of Differential CORDIC-based high-speed phase calculator for 3D Depth Image Extraction (3차원 Depth Image 추출용 Differential CORDIC 기반 고속 위상 연산기의 FPGA 구현)

  • Koo, Jung-youn;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.350-353
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    • 2013
  • In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

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Design of a 12-bit 1MSps SAR ADC using 0.18㎛ CMOS Process (0.18㎛ CMOS 공정을 이용한 12-bit 1MSps 연속 근사화 아날로그-디지털 변환기 설계)

  • Seong, Myeong-U;Choi, Seong-Kyu;Kim, Sung-Woo;Kim, Shin-Gon;Lee, Joo-Seob;Oh, Se-Moung;Seo, Min-Soo;Ryu, Jee-Youl
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.365-367
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    • 2013
  • 본 논문에서는 $0.18{\mu}m$ CMOS 공정 기술을 이용하여 12-bit 1MSps 연속 근사화 아날로그-디지털 변환기(Analog to Digital Converter : ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 진행하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 5.5mW였고, 입력 신호의 주파수가 100kHz일 때, SNDR은 70.03dB, 유효 비트수는 11.34bit의 결과를 보였다. 설계된 변환기는 $0.8mm{\times}0.7mm$ 크기로 레이아웃 되었다.

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Improved RFID Authentication Protocol Based on SSG (SSG기반 개선된 RFID 인증 프로토콜)

  • Park, Taek-Jin
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.4
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    • pp.311-317
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    • 2011
  • Recently, RFID is substituted for bar codes according to advance in the ubiquitous computing environments, but the RFID system has several problems such as security and privacy because it uses radio frequencies. Firstly, unauthorized reader can easily read the ID information of any Tag. Secondly, Attacker can easily fake the legitimate reader using the collected Tag ID information,such as the any legitimate tag. This paper proposed improved RFID authentication protocol based on SSG. SSG is organized only one LFSR and selection logic. Thus SSG is suitable for implementation of hardware logic in system with extremely limited resources such as RFID tag and it has resistance to known various attacks because of output bit stream for the use as pseudorandom generator. The proposed protocol is secure and effective because it is based on SSG.

Controller Design of a galvanometer for Laser Marking Equipment (레이저 마킹 장비를 위한 갈바노미터의 제어기 설계)

  • 방승현;홍선기;김수길;강태삼
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.17 no.3
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    • pp.25-31
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    • 2003
  • In this paper, proposed is a control system for a galvanometer which is widely used fer laser display, laser processing and marking systems. The galvanometer with mirror is modeled as a second-order dynamic system Based on frequency responses and time domain responses of the developed model, a conventional PID controller is designed And it is implemented using a DSP(TMS320C32) chip with precision A/D and D/A converters. Through frequency response and experimental results, it is convinced that the proposed control system works well in real environment. Furthermore it is very easy to be connected to any PC because of USB communication port, and the cost of the marking system can be lowered very much because the DSP do the all the jobs for generating font motion as well as controlling the galvanometer.

Design Technique of Register-based Asynchronous FIFO (레지스터 기반 비동기 FIFO 구조 설계 기법)

  • Lee, Yong-Hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.1038-1041
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    • 2005
  • In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

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Adaptive Image Coding Technique using HVS in Biorthogonal Wavelet Transform Domain (Biorthogonal 웨이브릿 변환영역에서 HVS를 이용한 적응 영상 부호화 기법)

  • 김응태;김형명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.10
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    • pp.1469-1482
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    • 1993
  • A new image coding technique has been proposed based on the wavelet transform. To achieve lower ceding rates and good qualities in reconstructed images, some of wavelet coefficients were removed by thresholding and quantized in accordance with the sensitivity of the human visual system(HVS). For each block of subimages in wavelet transform domain, block thresholding scheme has been used to remove the unimportant wavelet coefficients according to the frequency characteristic and statistical property of wavelet coefficients. The location information of quantized blocks and removed blocks were encoded using run-length coder which is effective for the exponential distribution. Quantized coefficients were encoded using variable length coder which matches well to their distribution. Simulation results show that the reconstructed images maintain high quality with the low bit rate, below 1.0 bits per pel.

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Transmit Power and Subcarrier Allocation Schemes for Downlink OFDM Systems with Multiple Relays (하향링크 다중 중계기 직교 주파수 분할 다중 시스템을 위한 송신 전력 및 부반송파 할당 기법)

  • Je, Hui-Won;Kim, Ik-Hyun;Lee, Kwang-Bok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.3A
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    • pp.281-289
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    • 2009
  • Wireless relay attracts great attention as a core technology of next generation wireless communication systems since it enables reliable communications and extends cell coverage by supporting shadowed users. In this paper, we Propose transmit power and subcarrier allocation scheme for downlink OFDM systems with multiple decode and forward (DF) relays to increase data rate with fixed bit error rate (BER) and sum power constraint. In simulation results, average data rate based on the proposed schemes are evaluated and compared to that of the other schemes. It is also shown that the performance loss of the proposed scheme is negligible compared to the optimal scheme, while its computational complexity is reduced considerably.

Improvement for Transmission Speed of G3 FAX (G3 팩스 전송속도 성능 향상에 관한 연구)

  • Kim, K.T.;Bae, J.I.;Jo, B.K.;Kim, J.B.
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.3204-3205
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    • 1999
  • G3 팩스가 G1 팩스나 G2 팩스와 구별되는 점은 문서 이미지를 스캔하여 얻은 아날로그 신호(전압)를 디지털 신호로 바꿔주는 A/D 변환과 여기서 얻어진 디지털 신호를 전송을 위해 다시 아날로그 신호(주파수, 위상 진폭)로 바꿔주는 모듈레이션 과정이 중간에 신호를 압축하여 표현하는 코딩 단계가 있다는 것이다. 따라서 G1 팩스나 G2 팩스에 비해 s훨씬 적은 신호를 가지고 문서 이미지를 표현할 수 있으며, 결과적으로 전송속도가 빨라지는 것이 된다. 표준 A4용지는 수평 방향으로 1728개의 픽셀, 수직방향으로 1145라인의 픽셀로 구성된다. 따라서 층 1,978,560($1728{\times}1145$) 비트의 데이터가 A4용지 한 장에 포함될 수 있는 것이다. 팩스가 이런한 표준 A4용지를 스캔하게될 경우 수캔되는 매 라인에는 1728개의 검은색(글자 및 그림) 및 흰색 (여백)픽 셀들이 존재한다. G3 팩스는 서로 다른 Run Length에 비교적 짧은 특정 코드를 미리 할당해 놓고 실제 픽셀들 대신 이러한 코드들을 모듈레이션해서 전송한다. 따라서 전송속도는 단축된다.

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Fixed-point Optimization of a Multi-channel Digital Hearing Aid Algorithm (다중 채널 디지털 보청기 알고리즘의 고정 소수점 연산 최적화)

  • Lee, Keun Sang;Baek, Yong Hyun;Park, Young Chul
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.2 no.2
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    • pp.37-43
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    • 2009
  • In this study, multi-channel digital hearing aid algorithm for low power system is proposed. First, MDCT(Modified Discrete Cosine Transform) method converts time domain of input speech signal into frequency domain of it. Output signal from MDCT makes a group about each channel, and then each channel signal adjusts a gain using LCF(Loudness Compensation Function) table depending on hearing loss of an auditory person. Finally, compensation signal is composed by TDAC and IMDCT. Its all of process make progress 16-bit fixed-point operation. We use fast-MDCT instead of MDCT for reducing system complexity and previously computed tables instead of log computation for estimating a gain. This algorithm evaluate through computer simulation.

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Performance Comparison of Baseband Modulation Methods in DS-CDMA Communication System (대역확산통신시스템에서 기저대역변조 방식에 따른 성능 비교)

  • 이성민;김환우
    • Journal of the Korea Institute of Military Science and Technology
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    • v.5 no.1
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    • pp.24-36
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    • 2002
  • It is important to use frequency resource effectively to support much more users, to maximize the DS-CDMA system performance. In this paper, we use MPSK, QAM, MFSK and PR coder as a baseband modulation method for DS-CDMA system. Increasing user's number, we compare the performance of each system using different baseband modulation method, by expecting BER performance. BPSK has generally good performance, in case of low power operation of terminal 8FSK has excellent performance relatively, PR has excellent performance when high power operation of terminal and also good for situation of excessive user's number. QAM is not suitable for DS-CDMA system.