• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1582-1589
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• 2006

A lock mechanism is essential for synchronization on the multiprocessor systems. The conventional queuing lock has two bus traffics that are the initial and retry of the lock-read. %is paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism, which has only one lock-read bus traffic command. The WPV mechanism accesses the shared data in the initial lock-read phase that is held in the pipelined protocol until the shared data is transferred. The nv mechanism also uses the cache state lock mechanism to reduce the locking overhead and guarantees the FIFO lock operations in the multiple lock contentions. In this paper, we also derive the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that about 50% of access time is reduced comparing with the conventional queuing lock mechanism.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.152-155
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• 1999

ATM은 다양한 종류의 실시간 및 비실시간 트래픽을 지원할 수 있도록 기존의 회선 교환망과 패킷 교환망의 장점을 수용하여 셀이라는 일정한 크기의 패킷을 비동기식 시분할 방식으로 전송하는 방식이다. 이와 같은 ATM은 STM가 달리 대역폭의 효율적인 할당이 가능하므로 기존의 망에서 다루고 있는 데이터 통신 서비스 외에도 고화질의 화상이나 동영상, 멀티미디어 트래픽 제어는 실시간 접속에 대한 서비스 품질(QoS)의 보장이 요구되므로 본 논문은 망내에서 트래픽 왜곡과 CBR/VBR 접속에 대한 트래픽의 일반적 패턴과 셀 큐잉 지연 범위를 획득하여 최악의 규잉 분석을 모델링할 수 있는 비트 스트림 트래픽 모델에 기반을 둔 트래픽 제어 기법이 비트 스트림 제어 알고리즘을 제안한다. 제안된 알고리즘은 정적 우선순위스케줄링과 FIFO 큐잉 스위치를 갖는 ATM 망에서 엄격한 실시간 통신 서비스를 제공할 수 있다.

• Journal of KIISE:Software and Applications
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• v.30 no.12
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• pp.1185-1192
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• 2003

In the component assembly and composition technique of software architecture, It is operated that the existing composition techniques based on architecture, ACME, Wright etc., used in FIFO with the direct connection structure between components through connector's Role. But, when the non-synchronizing request of components that have different characteristics occurs, the FIFO techniques is applied to the connector is difficult to process and operate effectively because of the high performance component waiting the sequence order if the low performance component is allocated first. Thus, the allocated request process according to the priority considering the characteristics of each call components in connector is necessary to improve the operation of assembled component. In this research, we extend the connector part that is available in multiplex connection structure based on existent Wright specification. For service process requested from component, the connector part is designed and implemented to operating with priority sequence through calculating the weight of CPU use rate, bean requesting process time and memory use rate among the efficiency elements of assembled components. To verify the efficiency if this designed connector, we implemented 20 samples EJB components that have different efficiency characteristics and applied these samples components to designed connector. The operating results with this designed connector show that the efficient operation of whole system is possible though the processing time takes 481ms more than the time of the existing FIFO techniques.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.