• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.43-48
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• 2010

In general, in order to reduce an initial cell searching time, W-CDMA systems adopt a three-step cell search scheme: slot synchronization, frame synchronization, and primary scrambling code identification. We consider the second step (frame synchronization), in which a coherent detection using P-SCH (primary synchronization channel) is possible. In this paper, we propose a new coherent detection scheme, where a first order recursive filter is used to enhance channel estimation performance. Computer simulation results indicate that the detection performance of the proposed scheme can be robust over large range of frequency offset.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.3
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• pp.169-175
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• 2002

This paper is about the hardness of the Election problem in asynchronous distributed systems in which processes can crash but links are reliable. The hardness of the problem is defined with respect to the difficulty to solve it despite failures. It is shown that problems encountered in the system are classified as three classes of problems: F (fault-tolerant), NF (Not fault-tolerant) and NFC(NF-completeness). Among those, the class NFC is the hardest problems to solve. In this paper, we prove that the Election problem is the most difficult problem which belongs to the class NFC.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.3
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• pp.40-47
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• 2011

This paper addresses the problem of fault detection and tolerance for asynchronous sequential machines using state feedback control. The considered asynchronous machine is affected by intermittent faults. When intermittent faults occur, the machine undergoes unauthorized state transitions and, for a finite duration, remains at the fault state, not responding to the change of the external input. In this paper, we postulate the scheme of detecting intermittent faults and present the existence condition and design algorithm for a robust state feedback controller that overcomes the adversarial effect of intermittent faults. We also undertake a comparative study between the previous control scheme for transient faults and the present strategy for intermittent faults. The design procedure for the proposed controller is described in a case study.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.47-55
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• 1999

In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.394-400
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• 2000

The main goal of synchronization is to guarantee exclusive access to shared data and critical sections, and then it makes parallel programs work correctly and reliably. Exclusive access restricts parallelism of parallel programs, therefor efficient synchronization is essential to achieve high performance in shared-memory parallel programs. Many techniques are devised for efficient synchronization, which utilize features of systems and applications. This paper shows the simulation results that existing synchronization methods have inefficiency under CC-NUMA(Cache Coherent Non-Uniform Memory Access) system, and then compares the performance of Freeze&Melt synchronization that can remove the inefficiency. The simulation results present that Test-and-Test&Set synchronization has inefficiency caused by broadcast operation and the pre-defined order of Queue-On-Lock-Bit (QOLB) synchronization to execute a critical section causes inefficiency. Freeze&Melt synchronization, which removes these inefficiencies, has performance gain by decreasing the waiting time to execute a critical section and the execution time of a critical section, and by reducing the traffic between clusters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.6
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• pp.698-706
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• 2016

Orthogonal frequency division multiplexing (OFDM) has high peak to power ratio (PAPR). High PAPR makes problems such as signal distortion and circuit cost increasing. To solve the problemsm several PAPR reduction methods have been proposed. However, synchronization and orthogonality in OFDM systems may be a limitation to reduce latency for 5G networks. Generalized frequency division multiplexing (GFDM) is one of the possible solutions for asynchronous and non-orthogonal systems, which are more preferable to reduce the latency. However, multiple subsymbols in GFDM result in more superposition in time domain, GFDM has higher PAPR. Selective mapping (SLM) is one of PAPR reduction techniques in OFDM, which uses phase shift. The PAPR of GFDM SLM is compared to conventional GFDM and OFDM SLM in terms of PAPR reduction enhancement via numerical simulations. In addition, the out-of-band performance is analyzed in the aspect of asynchronous condition interference.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.82-87
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• 2001

In this paper we described the generation method of interface logic which can be replace between IP and IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new \"Waveform Conversion Algorithm : Wave2VHDL\", if only mixed asynchronous timing waveform suggested which level type input and pulse type input for handshaking, we can convert waveform to flowchart and then replaced with VHDL code according to converted flowchart. Also, we assure that asynchronous electronic circuits for IP interface are generated by applying extracted VHDL source code from suggested algorithm to conventional domestic/abroad CAD Tool, and then we proved that coincidence simulation result and suggested timing diagram.g diagram.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.1
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• pp.1-8
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• 1979

This paper describes a simple asynchronous time dime division multiplexing system developed by means of a synchronous delta modulation. In realizing asynchronous multlplexlng system time author deals with a technique of multiplexing communication channels by reversing the polarity of output pulse and superimposing the channels at a certain time Interval. The results of experiments on the number of error pulses, signal-to-noise ratio and frequency characteristics have shown fair agreements with the theoretically predicted ones related to the system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.