• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.70-77
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• 2008

On the wireless sensor network MAC protocols, one of main issues is energy enciency. Since several asynchronous wireless sensor network MAC protocols with short preamble sampling scheme can be operated without setting the timing synchronization among neighbor nodes, it consumes a little energy for maintaining protocols. However, each node encounters either preamble or data overhearing problem, because each node wakes up in a different time and must check whether the frame is being sent to itself or not. To solve this overhearing problem, we newly propose B-MAC++ that can reduce the overhearing energy consumption by using short preambles with destination address and payload length. from simulation results, we show that the proposed B-MAC++ has advantageous in terms of power consumption efficiency over other asynchronous wireless sensor network MAC protocols.

• Journal of Broadcast Engineering
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• v.10 no.2
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• pp.174-181
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• 2005

In this paper, we proposed new fast scattered pilot synchronization techniques to reduce the burst synchronization time for the DVB-H receiving system with robustness. DVB-H terminals employ a TDM system called 'Time-Slicing' to reduce power consumption. In order to fully exploit the potential power reduction, the synchronization time for the DVB-H receiver must be very short. A typical DVB-T system uses the TPS Synchronization to determine the position of scattered pilots which are used for channel estimation, and it takes 68 OFDM symbol time. In this paper, several new fast scattered pilot synchronization techniques are proposed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.32-37
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• 2008

Satellite communication systems including the DVB-S2 (Digital Video Broadcasting - Satellite Version 2) system require operations under low signal-to-noise ratio (SNR) and large frequency offset values, and the initial frame synchronization process necessitates a robust correlation method. While a variety of conventional correlation structures exist for the initial synchronization, each method has different characteristics and performance in different channel environments. In this paper, we propose new correlation methods which exhibit enhanced performance in low SNR and large frequency offsets, and analyze their performance. The proposed methods use the magnitude sum and vector sum of extended differential correlation values, to maximize the correlation between the received signal and the synchronization sequence by using the spanned differential correlation result. The magnitude sum correlation method has better performance compared to conventional methods including the approximated ML (Maximum likelihood) method for SNR values below 4 dB with or without frequency offsets. The vector sum correlation method has improved performance over the magnitude sum method for channels with relatively small frequency offsets.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.4
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• pp.7-14
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• 2010

Stable-state behaviors of asynchronous sequential machines represented as finite state machines can be corrected by feedback control schemes. In this paper, we propose a state feedback control scheme for input/state asynchronous machines with uncertain transitions. The considered asynchronous machine is deterministic, but its state transition function is partially known due to model uncertainty or inner logic errors. The control objective is to compensate the behavior of the closed-loop system so that it matches a sub-behavior of a prescribed model despite uncertain transitions. Furthermore, during the execution of corrective action, the controller reflects the exact knowledge of transitions into the next step, i.e., the range of the behavior of the closed-loop system can be enlarged through learning. The design procedure for the proposed controller is described in a case study.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.