• Title/Summary/Keyword: 블록 합

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Implement and Experiment of Efficient Off-Chain (단방향 해시 함수를 활용한 효율적인 Off-chain Payment Channel 구현 및 실험)

  • Kim, Sun Hyoung;Jeong, Jae Yeol;Jeong, Ik Rae
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.29 no.6
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    • pp.1413-1424
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    • 2019
  • Cryptocurrency has limitations to be used as an actual payment method due to the scalability problem of the blockchain consensus protocol, and various off-chain solutions to solve these limitations are being studied. In this paper, we design an efficient off-chain payment channel using one-way hash function and implement the designed payment channel using Ethereum smart contract. In addition, the experiment was conducted to measure and analyze execution time and cost for each method by deploying it in the same environment as the previously implemented plasma MVP. As a result, compared with plasma MVP, the proposed solution was able to reduce the total cumulative time by about 34% and reduce the overall execution cost by about 41%.

An analysis of BER performance of LDPC decoder for WiMAX (WiMAX용 LDPC 복호기의 비트오율 성능 분석)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.771-774
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    • 2010
  • In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

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Detecting Dissolve Cut for Multidimensional Analysis in an MPEG compressed domain : Using DCT-R of I, P Frames (MPEG의 다차원 분석을 통한 디졸브 구간 검출 : I, P프레임의 DCT-R값을 이용)

  • Heo, Jung;Park, Sang-Sung;Jang, Dong-Sik
    • Journal of the Institute of Convergence Signal Processing
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    • v.4 no.3
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    • pp.34-40
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    • 2003
  • The paper presents a method to detect dissolve shots of video scene change detections in an MPEG compressed domain. The proposed algorithm uses color-R DCT coefficients of Ⅰ, P-frames for a fast operation and accurate detection and a minimum decoding process in MPEG sequences. The paper presents a method to detect dissolve shot for three-dimensional visualization and analysis of Image in order to recognize easily in computer as a human detects accurately shots of scene change. First, Color-R DCT coefficients for 8*8 units are obtained and the features are summed in a row. Second, Four-step analysis are Performed for differences of the sum in the frame sequences. The experimental results showed that the algorithm has better detection performance, such as precision and recall rate, than the existing method using an average for all DC image by performing four step analysis. The algorithm has the advantage of speed, simplicity and accuracy. In addition. it requires less amount of storage.

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Study on a Separator for the All-vanadium Redox Flow Battery (바나듐 레독스-흐름 전지용 격막에 관한 연구)

  • Lee, Sang-Ho;Kim, Joeng-Geun;Choi, Sang-Il;Hwang, Gab-Jin;Jin, Chang-Soo
    • Membrane Journal
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    • v.19 no.2
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    • pp.129-135
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    • 2009
  • The cation exchange membrane using the block co-polymer of polysulfone and polyphenylenesulfidesulfone was prepared for a separator of all-vanadium redox flow battery. The membrane property of the prepared cation exchange membrane was measured. The thermal stability of the prepared cation exchange analyzed by TG showed a more stable than that of Nafion117. The lowest measured membrane resistance, equilibrated in 1mol/L $H_2SO_4$ aqueous solution, $0.96{\cdot}cm^2$ at 3 cc of CSA (chlorosulfuricacid) which was introduction agent of ion exchange group. Electrochemical property of all-vanadium redox flow battery using the prepared cation exchange membrane was measured. Electromotive force in 100% of state of charge was 1.4 V which was that of all-vanadium redox flow battery, and cell resistance in charge and discharge at each state of charge had a low value compared with that of all-vanadium redox flow battery using Nafion117.

Intra Prediction Method by Quadric Surface Modeling for Depth Video (깊이 영상의 이차 곡면 모델링을 통한 화면 내 예측 방법)

  • Lee, Dong-seok;Kwon, Soon-kak
    • Journal of Korea Society of Industrial Information Systems
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    • v.27 no.2
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    • pp.35-44
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    • 2022
  • In this paper, we propose an intra-picture prediction method by a quadratic surface modeling method for depth video coding. The pixels of depth video are transformed to 3D coordinates using distance information. A quadratic surface with the smallest error is found by least square method for reference pixels. The reference pixel can be either the upper pixels or the left pixels. In the intra prediction using the quadratic surface, two predcition values are computed for one pixel. Two errors are computed as the square sums of differences between each prediction values and the pixel values of the reference pixels. The pixel sof the block are predicted by the reference pixels and prediction method that they have the lowest error. Comparing with the-state-of-art video coding method, simulation results show that the distortion and the bit rate are improved by up to 5.16% and 5.12%, respectively.

A 8b 1GS/s Fractional Folding-Interpolation ADC with a Novel Digital Encoding Technique (새로운 디지털 인코딩 기법을 적용한 8비트 1GS/s 프랙셔널 폴딩-인터폴레이션 ADC)

  • Choi, Donggwi;Kim, Daeyun;Song, Minkyu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.137-147
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    • 2013
  • In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

Poly(arylene ether ketone) block copolymer prepared through sulfonation process for polymer electrolyte membrane fuel cell (술폰화 공정을 통해 제조한 고분자 전해질형 연료전지용 폴리(아릴렌 이서 케톤) 블록 코폴리머)

  • Jang, Hyeri;Nahm, Keesuk;Yoo, Dongjin
    • Journal of Energy Engineering
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    • v.25 no.3
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    • pp.66-72
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    • 2016
  • In this study, a sulfonated poly(arylene ether ketone) block copolymer was prepared from hydrophilic oligomer and hydrophobic oligomer. The structure of the prepared membrane was characterized by $^1H$-NMR, FT-IR and GPC. The $M_w$(weight-average molecular weights) of the polymer was $209,700g\;mol^{-1}$ and the molecular weight distribution($M_w/M_n$) of 1.25 was obtained. The prepared membrane showed excellent thermal stability with gradual weight loss up to $200^{\circ}C$. The proton conductivity of SPAEK block copolymer reached the maximum of $9.0mS\;cm^{-1}$ at $90^{\circ}C$ under 100% relative humidity (RH). From the observed results, it is necessary to do more aggressive attempt to study the possibility of application as an ion-conductive composite electrolyte.

A Feasibility study on the Simplified Two Source Model for Relative Electron Output Factor of Irregular Block Shape (단순화 이선원 모델을 이용한 전자선 선량율 계산 알고리듬에 관한 예비적 연구)

  • 고영은;이병용;조병철;안승도;김종훈;이상욱;최은경
    • Progress in Medical Physics
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    • v.13 no.1
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    • pp.21-26
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    • 2002
  • A practical calculation algorithm which calculates the relative output factor(ROF) for irregular shaped electron field has been developed and evaluated the accuracy of the algorithm. The algorithm adapted two-source model, which assumes that the electron dose can be express as sum of the primary source component and the scattered component from the shielding block. Original two-source model has been modified in order to make the algorithm simpler and to reduce the number of parameters needed in the calculation, while the calculation error remains within clinical tolerance range. The primary source is assumed to have Gaussian distribution, while the scattered component follows the inverse square law. Depth and angular dependency of the primary and the scattered are ignored ROF can be calculated with three parameters such as, the effective source distance, the variance of primary source, and the scattering power of the block. The coefficients are obtained from the square shaped-block measurements and the algorithm is confirmed from the rectangular or irregular shaped-fields used in the clinic. The results showed less than 1.0 % difference between the calculation and measurements for most cases. None of cases which have bigger than 2.1 % have been found. By improving the algorithm for the aperture region which shows the largest error, the algorithm could be practically used in the clinic, since one can acquire the 1011 parameter's with minimum measurements(5∼6 measurements per cones) and generates accurate results within the clinically acceptable range.

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A Re-configurable 0.8V 10b 60MS/s 19.2mW 0.13um CMOS ADC Operating down to 0.5V (0.5V까지 재구성 가능한 0.8V 10비트 60MS/s 19.2mW 0.13um CMOS A/D 변환기)

  • Lee, Se-Won;Yoo, Si-Wook;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.60-68
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    • 2008
  • This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

Real-time Hand Region Detection based on Cascade using Depth Information (깊이정보를 이용한 케스케이드 방식의 실시간 손 영역 검출)

  • Joo, Sung Il;Weon, Sun Hee;Choi, Hyung Il
    • KIPS Transactions on Software and Data Engineering
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    • v.2 no.10
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    • pp.713-722
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    • 2013
  • This paper proposes a method of using depth information to detect the hand region in real-time based on the cascade method. In order to ensure stable and speedy detection of the hand region even under conditions of lighting changes in the test environment, this study uses only features based on depth information, and proposes a method of detecting the hand region by means of a classifier that uses boosting and cascading methods. First, in order to extract features using only depth information, we calculate the difference between the depth value at the center of the input image and the average of depth value within the segmented block, and to ensure that hand regions of all sizes will be detected, we use the central depth value and the second order linear model to predict the size of the hand region. The cascade method is applied to implement training and recognition by extracting features from the hand region. The classifier proposed in this paper maintains accuracy and enhances speed by composing each stage into a single weak classifier and obtaining the threshold value that satisfies the detection rate while exhibiting the lowest error rate to perform over-fitting training. The trained classifier is used to classify the hand region, and detects the final hand region in the final merger stage. Lastly, to verify performance, we perform quantitative and qualitative comparative analyses with various conventional AdaBoost algorithms to confirm the efficiency of the hand region detection algorithm proposed in this paper.