• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.2
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• pp.151-157
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• 2022

In this paper, the performance of various blockchain consensus algorithms was compared and analyzed as a method to increase the transaction cost and processing time during NFT transactions and to increase the transaction stability requirements that occur during smart contract execution. Network reliability and TPS are evaluation items for performance comparison. TPS and the stability of the Consensus algorithm are presented for three evaluation items. In order to establish a standardized expression for each evaluation item, the reliability of the node and the success rate of the smart contract were considered as variables in the calculation formula, and the performance of the consensus algorithm of the three groups, PoW/PoS, Paxos/Raft and PBFT, was compared under the same conditions. / analyzed. As a result of the performance evaluation, the network reliability of the three groups was similar, and in the case of the remaining two evaluation items, it was analyzed that the PBFT consensus algorithm was superior to other consensus algorithms. Through the performance evaluation equations and results of this study, it was analyzed that when the PBFT consensus processing process is reflected in the consensus process, the network reliability can be guaranteed and the stability and economic efficiency of the consensus algorithm can be increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of Advanced Navigation Technology
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• v.12 no.5
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• pp.437-443
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• 2008

In this paper, we derive the optimum number of users which can maximize the information theoretic sum capacity in multiuser OFDM virtual MIMO uplink system. In which, there are multiple antennas at the base station and a number of users with single transmit antenna. Pilot-assisted channel state estimation is assumed for a block fading channel and time-varying fading channel. We analyze the tradeoff between the multiplexing gain and pilot overhead especially in low SNR regime and conclude that the optimum number of users is min ($N_r$,LT/2 ) in frequency nonselective block fading channel and approximately equal to min ($N_r$, ${\lfloor}{\sqrt{LT+1}}-1{\rfloor}$) in time varying fading channel. assuming the same pilot and signal pwoer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.628-635
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• 2018

In this paper, we propose a fast motion estimation algorithm which is important in video encoding. So many fast motion estimation algorithms have been published for improving prediction quality and computational reduction. In the paper, we propose an algorithm that reduces unnecessary computation, while almost keeping prediction quality compared with the full search algorithm. The proposed algorithm calculates the sum of partial block matching error for each candidate, selects the candidates for the next step, compares the stability of optimal candidates with minimum error, and finds optimal motion vectors by determining the progress of the next step. By doing that, we can find the minimum error point as soon as possible and obtain fast computational speed by reducing unnecessary computations. Additionally, the proposed algorithm can be used with conventional fast motion estimation algorithms and prove it in the experimental results.

• Journal of Korean Society of Steel Construction
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• v.18 no.3
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• pp.349-359
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• 2006

This paper presents a new block stiffness matrix for the analysis an orthogonal Cartesian coordinate system. The displacement fields are defined using the first order shear deformable beam theory. The longitudinal displacement can be expressed as the sum of the projected plane deformation of the cross-section due to Timoshenko's beam theory and axial warping deformation due to modified Vlasov's thin-waled beam theory. The derived element takes into account flexural shear deformation and torsional warping deformation. Three different types of beam elements, namely, the two-noded, three-noded, and four-noded beam elements, are developed. The quadratic and cubic elements are found to be very efficient for the flexural analysis of laminated composite beams. The versatility and accuracy of the new element are demonstrated by comparing the numerical results available in the literature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.205-210
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• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.610-617
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• 2002

In this paper, a new intermediate view reconstruction technique by using a disparity estimation method based-on the adaptive matching window size is proposed. In the proposed method, once the feature values are extracted from the input stereo image, then the matching window size for the intermediate view reconstruction is adaptively selected in accordance with the magnitude of this feature values. That is, coarse matching is performed in the region having smaller feature values while accurate matching is carried out in the region having larger feature values by comparing with the predetermined threshold value. Accordingly, this new approach is not only able to reduce the mismatching probability of the disparity vector mostly happened in the accurate disparity estimation with a small matching window size, but is also able to reduce the blocking effect occurred in the disparity estimation with a large matching window size. Some experimental results on the 'Parts' and 'Piano' images show that the proposed method improves the PSNR about 2.32∼4.16dB and reduces the execution time to about 39.34∼65.58% than those of the conventional matching methods.