• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• Journal of Broadcast Engineering
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• v.13 no.6
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• pp.915-929
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• 2008

In this paper, we propose an algorithm for pixel-based disparity estimation with reliability in the multi-view image. The proposed method estimates an initial disparity map using edge information of an image, and the initial disparity map is used for reducing the search range to estimate the disparity efficiently. Furthermore, disparity-mismatch on object boundaries and textureless-regions get reduced by adaptive block size. We generated intermediate-view images to evaluate the estimated disparity. Test results show that the proposed algorithm obtained $0.1{\sim}1.2dB$ enhanced PSNR(peak signal to noise ratio) compared to conventional block-based and pixel-based disparity estimation methods.

• Journal of Digital Contents Society
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• v.9 no.4
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• pp.543-550
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• 2008

There exist many QoS problems such as delay and jitter for mobile streaming due to limited bandwidth. This paper proposed a transaction update method based on Fuzzy chunk to solve the problems. The proposed method updated a transaction, which is classified as a read or an update, using Fuzzy filtering. A chunk block is rearranged according to the fuzziness which is classified as better relevance for fuzziness greater than 0.8, relevance for fuzziness between 0.5 and 0.7, and less irrelevance for fuzziness less than 0.5. According to the simulation result for the rearranged chunk block, the proposed method has better performance than those of RBM(Randon Based method), DBM(Distance Based Method), and FBM(Frequency Based Method).

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.15-17
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• 2014

본 논문에서는 하드웨어의 제한된 자원을 이용하여 HEVC 코덱을 구현할 때 DCT 와 엔트로피 부호화를 사용하지 않고 율 및 왜곡값을 예측하여 고효율의 부호화를 수행하는 방법에 대하여 제안한다. HEVC 는 기존의 부호화기에 비하여 계층적 부호화 구조와 함께 큰 블록 크기를 갖는 DCT 와 엔트로피 부호화를 반복적으로 수행하기 때문에 하드웨어 구현 시 그 복잡도가 매우 크게 증가한다. 먼저 DCT 는 하다마드변환 행렬과 또 다른 정규 직교 변환 행렬의 곱으로 표현될 수 있는 성질을 이용하여 부호화 변환 시 생성된 하드마드변환 행렬에 저복잡도의 정규 직교 변환 행렬을 곱하여 DCT 변환 계수를 생성한 후 변환 및 양자화를 수행한다. 왜곡값의 경우, 이 때 생성된 양자화 계수와 변환 계수 간의 차이를 변환도메인에서 제곱합을 이용하여 계산하여 역변환을 생략함으로써 복잡도를 감소시킬 수 있다. 또한 텍스처에 대한 비트율 예측은 각 CU 블록내의 양자화 계수의 수를 더하여 계산하여 엔트로피를 수행하지 않고 예측할 수 있다. 그리고 비 텍스처에 대한 비트율 예측의 경우 움직임벡터의 비트에 대한 Pseudo CABAC 코드를 수행하여 예측할 수 있다. 이러한 저 복잡도의 텍스처 및 비텍스처 비트와 왜곡을 예측함으로써 하다마드변환만을 이용하여 부호화하였을 때에 비해 최대 33%의 비트율 감소를 얻을 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.7
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• pp.683-693
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• 2011

In this paper, a design of high current and broad-band microwave bias-tee was presented for a stable bias of a high power amplifier. An input impedance of bias-tee should be shown to 50 ohm with the wideband in order to be stably-biased the amplifier. For this design of the bias-tee, a capacitor of bias-tee for a DC block was designed with a high wide-band admittance by a parallel sum of capacitors, and a inductor for a RF choke and a DC feeding was designed with a high wide-band impedance by a series sum of inductors. As this inductor and capacitor for the sum has each SRF, band-limitation of lumped element was driven from SRF. This limitation was overcome by control of a resonance's quality factor with adding a resistor. 1608 SMD chips for design's element was mounted on the this pattern for the designed bias-tee. The fabricated bias-tee presented 10 dB of return loss and wide-band about 50 ohm input impedance at 10 MHz~10 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.876-884
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• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.

• The Journal of Korean Academy of Prosthodontics
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• v.48 no.2
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• pp.143-150
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• 2010

Purpose: The purpose of this study is to fabricate the new zirconia block (CNU block) and to evaluate fit of core and porcelain veneered zirconia crown. Material and methods: The experimental blocks were fabricated from the commercial ytrria-stabilized zirconia powder (KZ-3YE Type A). The powder was uniaxial pressing and the green bodies were conducted using the Cold Isostatic Pressing. The zirconia blocks were presintered at $1040^{\circ}C$ and the final sintering was performed at $1450^{\circ}C$. The Kavo Everest ZS $blank{(R)}$ (KaVo, Biberach/ $Ri{\beta}$.) was used as a control group. The linear shrinkage of CNU block and Kavo block were compared. Twenty-one cores for porcelain veneered crowns were fabricated with CAD/CAM system ($Everest{(R)}$, Biberach/ $Ri{\beta}$.). Group I; seven cores fabricated from Kavo blocks, Group II; seven cores fabricated from CNU blocks, Group III; seven cores from CNU blocks and porcelain veneering for crowns. All specimens were cemented and sectioned into two planes; diagonal and bucco-lingual. The measurement of the marginal, internal, and occlusal fit was carried out using SEM ($S-4800^{(R)}$) at $30{\times}$. The results were analyzed by one-way ANOVA test. Results: The linear shrinkage of the CNU block and the KaVo block was 19.00% and 20.09%. The marginal gap of cores ($29.67{\pm}6.58{\mu}m$) fabricated from CNU blocks showed significantly smaller than that of the cores of Kavo blocks ($36.84{\pm}7.18{\mu}m$) (P < .05). The internal gaps of the porcelain veneered crowns ($32.23{\pm}6.33{\mu}m$) were larger than those of the other two groups ($37.57{\pm}6.81{\mu}m$ and $38.14{\pm}6.81{\mu}m$). Conclusion: No statistically significant difference was found in between experimental groups and control group. The experimental groups in marginal gap showed significantly smaller than the control group.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.44-53
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• 2010

The H.264/AVC has been designed to use 9 directional intra prediction modes for removing spatial redundancy. It also employs high correlation between neighbouring block modes in sending mode information. For indication of the mode, smaller bits are assigned for higher probable modes and are compressed by predicting the mode with minimum value between two prediction modes of neighboring two blocks. In this paper, we calculated the statistical probability of prediction modes of the current block to exploit the correlation among the modes of neighboring two blocks with several test video sequences. Then, we made the probable prediction table that lists 5 most probable candidate modes for all possible combinatorial modes of upper and left blocks. By using this probability table, one of 5 higher probable candidate modes is selected based on RD-optimization to reduce computational complexity and determines the most probable mode for each cases for improving compression performance. The compression performance of the proposed algorithm is around 1.1%~1.50%, compared with JM14.2 and we achieved 18.46%~36.03% improvement in decoding speed.