• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.536-546
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• 2006

Painterly animation is a method that expresses painterly images with a hand-painted appearance from a video, and the most crucial element for it is the temporal coherence of brush strokes between frames. A motion map is proposed in this paper as a solution to the issue of maintaining the temporal coherence in the brush strokes between the frames. A motion map is the region that frame-to-frame motions have occurred. Namely, this map refers to the region frame-to-frame edges move by the motion information with the motion occurred edges as a starting point. In this paper, we employ the optical flow method and block-based method to estimate the motion information. The method that yielded the biggest PSNR using the motion information (the directions and magnitudes) acquired by various methods of motion estimation has been chosen as the final motion information to form a motion map. The created motion map determine the part of the frame that should be re-painted. In order to express painterly images with a hand- painted appearance and maintain the temporal coherence of brush strokes, the motion information was applied to only the strong edges that determine the directions of the brush strokes. Also, this paper seek to reduce the flickering phenomenon between the frames by using the multiple exposure method and the difference map created by the difference between images of the source and the canvas. Maintenance of the coherence in the direction of the brush strokes was also attempted by a local gradient interpolation to maintain the structural coherence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of KIISE:Information Networking
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• v.29 no.1
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• pp.86-96
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• 2002

In video conferencing system using H.263 encoding and decoding time is as important as compression rate is. To reduce encoding time, a number of methods were proposed. We use a method of them that reduces the computational complexity in motion estimation. The complexity is determined by three factors, such as a cost function, a search range parameter, and a motion search algorithm. In fact, it takes a lot of time to encode the video data on account of the cost function factor. That's the reason that we use the factor to reduce encoding time. In this paper, we tried to reduce total encoding time by reducing the number of calling the cost function. In case of a little moving, our algorithm enabled faster motion searching than TSS(Three Step Search) and NTSS(New TSS). Here, we called the algorithm by an ITSS(Improved TSS) that improves a shortcoming of NTSS requiring more checkpoints than TSS. For an experimentation, our algorithm was compared to other algorithms using PSNR, file size and SAD call times.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.67-74
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• 2013

Approximate string matching problems have been studied in diverse fields. Recently, fast approximate string matching algorithms are being used to reduce the time and costs for the next generation sequencing. To measure the amounts of errors between two strings, we use a distance function such as the edit distance. Given two strings X(|X| = m) and Y(|Y| = n) over an alphabet ${\Sigma}$, the edit distance between X and Y is the minimum number of edit operations to convert X into Y. The edit distance between X and Y can be computed using the well-known dynamic programming technique in O(mn) time and space. The edit distance also can be computed using the Four-Russians' algorithm whose preprocessing step runs in $O((3{\mid}{\Sigma}{\mid})^{2t}t^2)$ time and $O((3{\mid}{\Sigma}{\mid})^{2t}t)$ space and the computation step runs in O(mn/t) time and O(mn) space where t represents the size of the block. In this paper, we present a parallelized version of the computation step of the Four-Russians' algorithm. Our algorithm computes the edit distance between X and Y in O(m+n) time using m/t threads. Then we implemented both the sequential version and our parallelized version of the Four-Russians' algorithm using CUDA to compare the execution times. When t = 1 and t = 2, our algorithm runs about 10 times and 3 times faster than the sequential algorithm, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Proceedings of the Membrane Society of Korea Conference
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• 1998.10a
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• pp.70-72
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• 1998

1. 서론 : 최근에 폐수나 지하수 및 음용수에 존재하는 휘발성 유기화합물(Volatile Prganic Compound, VOC)는 심각한 환경오염이 주범이 되고 있다. 이러한 문제를 해결하는 방법으로 흡착, 증류, air stripping 등의 여러 가지 분리기술이 제시되어 왔다. 그러나 전통적인 방법들은 분리된 오염물질이 제2의 상으로 전이된다는 점에서 또 다른 분리공정을 필요로 하는 단점을 지니고 있다. 이에 반해 투과증발공정은 추가적인 분리과정이 없이 효율적으로 오염된 물속의 유기용매를 제거한다는 점에서 많은 관심을 모으고 있다. 이미 알려진 이러한 VOC 제거에는 소수성이면서 고무상인 고분자가 우수한 특성을 가지는 것으로 밝혀졌고 그 중에서 실록산계 고분자가 아주 효과적인 것으로 알려져 있다. 그러나 이러한 실록산계 고분자는 기계적 강도가 약하여 필름의 박막형성능력이 떨어지는 것으로 알려져 있어 이러한 단점을 보완하기 위해 가교구조의 도입이나 공중합체의 구조를 도입하는 연구가 많이 수행되어 왔다. 이러한 연구의 한 방법으로 실록산-아미드공중합체를 이용하여 투과증발에 적용한 연구는 수행되어 왔다. 이들의 제막방법으로 주로 실록산다이아민/방향족다이아민의 비를 달리하거나 실록산다이아민의 분자량의 변화를 달리하면서 실록산-이미드 블록 또는 그래프트중합체를 제조하는 방법을 사용하였다. 이 실험에서는 주로 실록산-이미드의 비율이 낮아지면 유기용매의 선택성에서 물의 선택성으로 바뀌는 percolation point가 관찰되며 이것은 실록산-이미드의 비율이 낮을수록 물속의 유기용매의 제거에 유리하다는 것을 보여준다. 이에 따라 실록산다이아민과 다이안하이드라이드만을 사용한 실록산이미드막이 추천되나 여기에 대한 투과특성연구는 전혀 이루어지지 않았다.정육점이었고 백화점과 재래닭 사육장에서 직접구입도 하고 있었다. 구입 동기는 가족들이 좋아하고 영양가를 생각한다가 62%였으며 구입정보는 주위사람의 권유로 구입하고 있었다. $\bigcirc$ 구입할 때 중점적으로 살펴보는 사항은 신선도와 순수재래종 여부, 위생상태였다. 한편 소비자가 언제나 구입할 수 없다는 의견이 85.2%나 되어 원활한 공급과 시장조성이 아직 정착되지 않고 있었다. $\bigcirc$ 현재 유통되고 있는 재래종닭은 소비자 대부분이 잡종으로 인식하고 있었으며, 재래종과 일반육계와의 구별은 깃털색, 피부색, 정강이색등 외관상으로 구별하고 있었다. 체중에 대한 반응은 너무 작다는 의견이었고, 식품으로의 인식도는 비교적 고급식품으로 인식하고 있다. $\bigcirc$ 재래종닭고기의 브랜드화에 대한 견해는 젊고 소득이 높은 계층에서 브랜드화의 필요성을 강조하고 있다. $\bigcirc$ 재래종달걀의 소비형태는 대부분의 소비자가 좋아하였으나 아직 먹어보지 못한 응답자가 많았다. 재래종달걀의 맛에 대해서는 고소하고 독특하여 차별성을 느끼고 있었다. $\bigcirc$ 재래종달걀의 구입장소는 계란판매점(축협.농협), 슈퍼, 백화점, 재래닭 사육 농장등 다양하였으며 포장단위는 10개를 가장 선호하였고, 포장재료는 종이, 플라스틱, 짚의 순으로 좋아하였다. $\bigcirc$ 달걀의 가격은 200원정도를 적정하다고 하였으며, 크기는 (평균 52g)는 가장 적당하다고 인식하고 있으며, 난각색은 대부분의 응답자가 갈색을 선호하였다. $\bigcirc$ 재래종달걀의 구입시 애로사항은 믿을수 없고, 구입장소를 몰라서, 값

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.565-568
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• 2014

This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.

• Journal of the Korean Geosynthetics Society
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• v.21 no.2
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• pp.57-65
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• 2022

This study simulated the shock wave propagation through the tamping material between explosives and hole wall at blasting works and verified the effect of tamping materials. The Arbitrary Lagrangian-Eulerian(ALE) method was selected to model the mixture of solid (Lagrangian) and fluid (Eulerian). The time series analysis was carried out during blasting process time. Explosives and tamping materials (air or water) were modeled with finite element mesh and the hole wall was assumed as a rigid body that can determine the propagation velocity and shock force hitting the hole wall from starting point (explosives). The numerical simulation results show that the propagation velocity and shock force in case of water were larger than those in case of air. In addition, the real site at blasting work was modeled and simulated. The rock was treated as elasto-plastic material. The results demonstrate that the instantaneous shock force was larger and the demolished block size was smaller in water than in air. On the contrary, the impact in the back side of explosives hole was smaller in water, because considerable amount of shock energy was used to demolish the rock, but the propagation of compression through solid becomes smaller due to the damping effect by rock demolition. Therefore, It can be proven that the water as the tamping media was more profitable than air.

• Journal of the Korea institute for structural maintenance and inspection
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• v.11 no.6
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• pp.121-130
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• 2007

In this paper, large scale experimental model tests were performed to investigate the distribution of earth pressure acting on embedded rigid pipes having different bedding conditions. For these tests, very light weighted EPS blocks were installed at top and bottom of the rigid pipe and Jumunjin Standard Sand was used as a ground material. As results of model tests, for the case of no bedding on the pipe, the measured pressure at the bottom of the pipe was $4.96_{tf/m^2}$ whereas they were in the range of $1.87{\sim}4.96_{tf/m^2}$ in the case of EPS beddings being installed at the top and the bottom of the pipe. Therefore, for the case of EPS bedding being installed, the ratio of reduced pressures acting on the pipe, compared with the case of no EPS beddings, were in the rage of 16~62%. As a result of parametric test with changing the locations of EPS bedding, the trend of reducing the stress acting on the pipe was in the order of bottom bedding, top bedding, and top and bottom bedding. Effect of bedding positions on the reduced magnitude of acting pressure on the pipe was more significant in the case of top bedding than in the case of the bottom bedding.

• Journal of Periodontal and Implant Science
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• v.30 no.2
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• pp.213-231
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• 2000

이 연구의 목적은 다공성의 CPP 내부에 쥐의 장골의 골수에서 유래된 세포를 접종하고 3차 원적으로 배양하여 CPP가 골 형성을 위한 조직공학의 지지체로 적용가능한가를 연구하는 것과 Calcium PolyPhosphate(CPP)의 돌연변이 유발성을 검사하는 것이다. 무수 ($Ca(H_2PO_4)$)를 condensation하여 무결정의 ($Ca(PO_3)$)를 얻고 이를 용융하고 냉각시킨 후 분쇄하여 Calcium polyphosphate(CPP) powder를 얻었다. 다공성의 CPP는 5% $SiO_2$를 첨가하여 sponge 형태로 $450-550{\mu}m$ 소공의 크기를 가지는 것과(CPP-45ppi) $200-300{\mu}m$의 소공의 크기를 가지는 것(CCP-60ppi) 2가지로 제작하였다. 각각의 CPP matrices는 $5mm{\times}5mm{\times}1mm$의 블록 형태로 만들었다. 체중 100g 내외의 백서에서 장골(femur, tibia)을 채취하여 백서의 장골 골수 세포를 분리하여 배양한 후 24well에 CPP block을 넣고 CPP block 당 $10^5$개의 배양한 세포를 접종하였다. 배양 1, 7, 14, 및 21 일째에 각 well에서 trypsin EDTA를 이용하여 2회 반복하여 cell을 분리하였고, 원심분리한 후 hemacytometer로 측정하였다. 또, 45ppi와 60ppi, 그 리 고 Tissue Culture Polystyrene(control group)에 접종, 배양된 세포들의 염기성 인산분해효소활성도를 배양 7, 14, 및 21 일째에 각각 측정하였다. 각 기간별로 배양된 세포-CPP 혼합체내에서 세포의 부착 및 증식과 형성된 조직의 3차원적 형태를 관찰하기 위하여 주사전자현미경하에서의 관찰하였다. CPP의 돌연변이 유발성 검사 (mutagenicity test)를 위해 hypoxanthine-guanine phosphoribosyl transferase(HPRT) assay를 하였다. NIH3T3 cell line과 CHO-K1 cell line으로 각각 $1000{\mu}g/m{\ell}$, $100{\mu}g/m{\ell}$, $10{\mu}g/m{\ell}$ 그리고 $1{\mu}g/m{\ell}$의 CPP 농도에서 측정하였다. 통계적 분석을 위해서 모든 측정은 각군당 4개체 이상 시험하였고, 각 측정값은 평균값${\pm}$표준편차로 나타내었다. 각 군간의 통계적 유의성 검정을 위해서 Analysis of variance(ANOVA)를 이용하였고 Tukey의 방법으로 사후분석을 실시하였다. 제작된 CPP matrices 소공들이 서로간에 연결이 잘 되어있는 형태였다. 두 가지로 제조된 CPP(45ppi와 60ppi) 모두에서 세포의 부착이 잘 일어났고, 부착된 세포의 분열도 잘 일어났다. 2 가지의 CPP 모두에서 7, 14, 21일째의 세포 수는 1일째에 비해 유의성 있게 증가하였다(P<0.01). 3차원적 구조인 Calcium PolyPhosphate에서 배양한 세포는 24well dish(tissue culture polystyrene)에서 평면적으로 배양한 대조군의 세포에서 보다 염기성 인산분해효소 (Alkaline Phosphatase)를 유의성 있게 높게 나타냈다. 주사전자현미경에서 세포-CPP 혼합체를 관찰한 결과, CPP block에 세포들이 잘부착되어 있었고, 시간이 지남에 따라 세포가 여러 층을 형성하면서 뭉치는 현상을 보였다. 또, HPRT assay 결과 , Calcium PolyPhosphate는 돌연변이 유발성을 보이지 않았다. 이상의 결과로 볼 때 CPP에는 세포부착이 잘 일어나고, 지지체 상에서 세포의 분열도 활발하게 일어나므로 골조직을 위한 조직공학의 우수한 지지체가 될 수 있을 것으로 사료된다.