• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.97-100
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• 2007

In order to overcome many defects in the current JPEG standard of still image compression, the new JPEG2000 standard has been development. The JPEG2000 standard is based on the principles of DWT and EBCOT Entropy Coding. EBCOT(Embedded block coding with optimized truncation) is the most important technology in the latest image-coding standard, JPEG2000. However, EBCOT occupies the highest computation time to operate bit-level processing. Therefore, many researches have achieved methods to minimize computation speed of EBCOT. Thus, this paper proposes the method of context-extraction that improves computational architecture. This paper proposes efficient context coding method. The proposed algorithm would apply to hard-wired JPEG2000 Encoder that is used for compression of high resolution image.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1672-1686
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• 2013

In this paper, we propose a hybrid super-resolution algorithm robust to cut-change. Existing single-frame based super-resolution algorithms are usually fast, but quantity of information for interpolation is limited. Although the existing multi-frame based super-resolution algorithms generally robust to this problem, the performance of algorithm strongly depends on motions of input video. Furthemore at boundary of cut, applying of the algorithm is limited. In the proposed method, we detect a define boundary of cut using cut-detection algorithm. Then we adaptively apply a single-frame based super-resolution method to detected cut. Additionally, we propose algorithms of normalizing motion vector and analyzing pattern of edge to solve various problems of existing super-resolution algorithms. The experimental results show that the proposed algorithm has better performance than other conventional interpolation methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.343-350
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• 2010

In the existing design of web server architecture, data encryption technique is used to keep the reliability, stability, and safety of web service. But the use of data encryption technique wastes the work of cpu while decreasing throughput of web server and increasing average response time so that it shows negative effect on the capacity of web application server. Also, the latest web applications require security and safety for the safe internet communication. Therefore, this paper suggests the improved web server which uses thread pool and Non-blocking I/O adding new web service modules to the existing web server for the safe web service, provides reliability and safety to show the safe web service capacity. And we compare and evaluate the safety and capacity through experiment on the existing traditional Tomcat based web server and the proposed system to evaluate the safety and capacity of the proposed web server system.

• Journal of IKEEE
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• v.26 no.1
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• pp.27-35
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• 2022

This paper proposes an ultrasound vessel-pattern imaging algorithm with low computational complexity. The proposed imaging algorithm reconstructs blood-vessel patterns by only detecting blood flow, and can be applied to a real-time signal processing hardware that extracts an ultrasonic finger-vessel pattern. Unlike a blood-flow imaging mode of typical ultrasound medical imaging device, the proposed imaging algorithm only reconstructs a presence of blood flow as an image. That is, since the proposed algorithm does not use an I/Q demodulation and detects a presence of blood flow by accumulating an absolute value of the clutter-filter output, a structure of the algorithm is relatively simple. To verify a complexity of the proposed algorithm, a simulation model for finger vessel was implemented using Field-II program. Through the behavioral simulation, it was confirmed that the processing time of the proposed algorithm is around 54 times less than that of the typical color-flow mode. Considering the required main building blocks and the amount of computation, the proposed algorithm is simple to implement in hardware such as an FPGA and an ASIC.

• The KIPS Transactions:PartB
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• v.9B no.3
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• pp.359-368
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• 2002

In this paper, we propose effective boundary line extraction algorithm for moving objects by matching error image and moving vectors, and fast tracking algorithm for moving object by partial boundary lines. We extracted boundary line for moving object by generating seeds with probability distribution function based on Watershed algorithm, and by extracting boundary line for moving objects through extending seeds, and then by using moving vectors. We processed tracking algorithm for moving object by using a part of boundary lines as features. We set up a part of every-direction boundary line for moving object as the initial feature vectors for moving objects. Then, we tracked moving object within current frames by using feature vector for the previous frames. As the result of the simulation for tracking moving object on the real images, we found that tracking processing of the proposed algorithm was simple due to tracking boundary line only for moving object as a feature, in contrast to the traditional tracking algorithm for active contour line that have varying processing cost with the length of boundary line. The operations was reduced about 39% as contrasted with the full search BMA. Tracking error was less than 4 pixel when the feature vector was $(15\times{5)}$ through the information of every-direction boundary line. The proposed algorithm just needed 200 times of search operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.275-286
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• 2008

Fast File System(FFS) utilizes large disk bandwidth to improve the write performance of large files. One way to improve the performance is to write multiple blocks of a large file at a single disk I/O through the disk bandwidth. However, rather than disk bandwidth, the performance of small file writes is limited by disk access times significantly impacted by disk movements such as disk seek and rotation because FFS writes each of small files at a single disk write. We propose CW-FFS (Co-Writing Fast File System) to improve the write performance of small files by minimizing the disk movements that are needed to write small files to disks. Its key technique called co-writing scheme is to dynamically collect multiple small files named by a given directory and then write them at a single disk I/O to contiguous disk locations. Co-writing several small files at a single disk I/O reduces multiple disk movements that are needed for small file writes to one single disk movement, thus increasing the overall write performance of write-intensive applications. Furthermore, a file allocation scheme is introduced to prevent co-writing scheme from having a negative impact on disk spatial locality of small files named by a given directory. The measurement of our technique implemented in the OpenBSD 4.0 shows that CW-FFS increases the performance of small file writes over FFS in the range from 5 to 35% in the Postmark benchmark.