• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.825-828
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• 2006

The most commonly used techniques for image magnification are interpolation based. However, the magnified images produced by this technique often appear blocking and blurring phenomenon when the image is enlarged. In this paper, we enhanced image magnification algorithm using edge information. The proposed algorithm not used interpolation based but by using sub-band of input image in extrapolation. According to mapping relationship in pyramid, we calculated up-band information to magnify. In experiments, the proposed model shows solved the problem of image loss like the blocking and blurring phenomenon. As the result, it is faster and higher resolution than traditional magnification algorithms.

• Annual Conference of KIPS
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• 2004.05a
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• pp.105-108
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• 2004

다단계 보안데이터베이스 시스템에서 기본적인 병행수행 제어 기법들은 비밀채널과 교착상태등과 같은 문제들이 발생하였다. 이에 직렬화 순서를 동적으로 재조정함으로서 해결하려는 방안이 있었지만, 알고리즘의 복잡성으로 인해 오버 헤드와 많은 수행시간이 필요하게 되었고, 이에 따라 많은 양의 시스템 자원과 높은 사양의 시스템을 요구하게 되었다. 또한 이러한 방법은 다중 버전을 사용함으로서 추가적인 관리비용이 높게 되었고, 각각의 트랜잭션이 지연 및 재수행이란 불필요한 과정을 반복하게 되었다. 따라서 본 논문에서는 제안한 알고리즘은 데이터베이스의 용도에 맞게 직렬화 순서를 보장하여 스케줄을 관리하는 요청 2단계 로킹기법(Request Two-phase Locking)으로서 이는 2단계 로킹기법의 기본원리에 요청로크를 사용함으로 보다 효율적으로 병행제어를 할 수 있다. 여기서 요청로크는 각각의 트랜잭션 스케줄에 로크획득 및 해제를 병행수행제어의 필요에 따라 유동적으로 할 수 있으며, 읽기로크, 쓰기로크, 요청로크라는 3가지 로킹모드를 통해 대처방안을 마련함으로서, 충돌을 방지하며, 충돌연산의 특성에 따라 직렬화 순서를 동적으로 조정함으로 블록킹을 막는 병행제어를 응용하여 병렬성을 유지한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.6
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• pp.1035-1043
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• 2022

With the spread of the Internet of Things (IoT), cloud computing, and big data, the need for high-speed encryption for applications is emerging. GPU optimization can be used to validate cryptographic analysis results or reduced versions theoretically obtained by the GPU in a reasonable time. In this paper, PIPO lightweight encryption implemented in various environments was implemented on GPU. Optimally implemented considering the brute force attack on PIPO. In particular, the optimization implementation applying the bit slicing technique and the GPU elements were used as much as possible. As a result, the implementation of the proposed method showed a throughput of about 19.5 billion per second in the RTX 3060 environment, achieving a throughput of about 122 times higher than that of the previous study.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.1-17
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• 2008

Recently, the object based storage devices systems(OSDs) have been actively researched. They are different from existing block based storage systems(BSDs) in terms of the storage unit. The storage unit of the OSDs is an object that includes the access methods, the attributes of data, the security information, and so on. The object has no size limit and no influence on the internal storage structures. Therefore, the OSDs improve the I/O throughput and the scalability. But the backup systems for the OSDs still use the existing backup techniques for the BSDs. As a result, they need much backup time and do not utilize the characteristics of the OSDs. In this paper, we design and implement a new object based backup system that utilizes the features of the OSDs. Our backup system significantly improves the backup time over existing backup systems because the raw objects are directly transferred to the backup devices in our system. It also restores the backup data much faster than the existing systems when system failures occur. In addition, it supports various types of backup and restore requests.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.84-95
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• 2011

In this paper, we present a deblocking algorithm that removes grid and staircase noises, which are called "blocking artifacts", occurred in the compressed satellite images. Particularly, the given satellite images are compressed with equal quantization coefficients in row according to region complexity, and more complicated regions are compressed more. However, this approach has a problem that relatively less complicated regions within the same row of complicated regions have blocking artifacts. Removing these artifacts with a general deblocking algorithm can blur complex and undesired regions as well. Additionally, the general filter lacks in preserving the curved edges. Therefore, the proposed algorithm presents an adaptive filtering scheme for removing blocking artifacts while preserving the image details including curved edges using the given quantization step size and content analysis. Particularly, WLFPCA (weighted lowpass filter using principle component analysis) is employed to reduce the artifacts around edges. Experimental results showed that the proposed method outperforms SA-DCT in terms of subjective image quality.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.69-78
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• 2017

Shannon of the 5G smartphone and Fourier of the signal processing meet in the sampling theorem (2 times the highest frequency 1). In this paper, the initial Shannon Theorem finds the Shannon capacity at the point-to-point, but the 5G shows on the Relay channel that the technology has evolved into Multi Point MIMO. Fourier transforms are signal processing with fixed parameters. We analyzed the performance by proposing a 2N-1 multivariate Fourier-Jacket transform in the multimedia age. In this study, the authors tackle this signal processing complexity issue by proposing a Jacket-based fast method for reducing the precoding/decoding complexity in terms of time computation. Jacket transforms have shown to find applications in signal processing and coding theory. Jacket transforms are defined to be $n{\times}n$ matrices $A=(a_{jk})$ over a field F with the property $AA^{\dot{+}}=nl_n$, where $A^{\dot{+}}$ is the transpose matrix of the element-wise inverse of A, that is, $A^{\dot{+}}=(a^{-1}_{kj})$, which generalise Hadamard transforms and centre weighted Hadamard transforms. In particular, exploiting the Jacket transform properties, the authors propose a new eigenvalue decomposition (EVD) method with application in precoding and decoding of distributive multi-input multi-output channels in relay-based DF cooperative wireless networks in which the transmission is based on using single-symbol decodable space-time block codes. The authors show that the proposed Jacket-based method of EVD has significant reduction in its computational time as compared to the conventional-based EVD method. Performance in terms of computational time reduction is evaluated quantitatively through mathematical analysis and numerical results.

• Journal of Broadcast Engineering
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• v.26 no.4
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• pp.429-440
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• 2021

With the recent development of deep convolutional neural network learning, deep learning techniques applied to single image super-resolution are showing good results. One of the existing deep learning-based super-resolution techniques is RDN(Residual Dense Network), in which the initial feature information is transmitted to the last layer using residual dense blocks, and subsequent layers are restored using input information of previous layers. However, if all hierarchical features are connected and learned and a large number of residual dense blocks are stacked, despite good performance, a large number of parameters and huge computational load are needed, so it takes a lot of time to learn a network and a slow processing speed, and it is not applicable to a mobile system. In this paper, we use the residual dense structure, which is a continuous memory structure that reuses previous information, and the residual dense channel attention block using the channel attention method that determines the importance according to the feature map of the image. We propose a method that can increase the depth to obtain a large receptive field and maintain a concise model at the same time. As a result of the experiment, the proposed network obtained PSNR as low as 0.205dB on average at 4× magnification compared to RDN, but about 1.8 times faster processing speed, about 10 times less number of parameters and about 1.74 times less computation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of KIISE:Information Networking
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• v.30 no.1
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• pp.134-142
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• 2003

We present an ATM switch architectures based on the multistage interconnection network(MIN) for the efficient multicast traffic control. Many of these applications require multicast connections as well as point-to-point connections. Muiticast connection in which the same message is delivered from a source to arbitrary number of destinations is fundamental in the areas such as teleconferencing, VOD(video on demand), distributed data processing, etc. In designing the multicast ATM switches to support those services, we should consider the fairness(impartiality) and priority control, in addition to the overflow problem, cell processing with large number of copies, and the blocking problem. In particular, the fairness problem which is to distribute the incoming cells to input ports smoothly is occurred when a cell with the large copy number enters upper input port. In this case, the upper input port sends before the lower input port because of the calculating method of running sum, and therefore cell arrived into lower input port Is delayed to next cycle to be sent and transmission delay time becomes longer. In this paper, we propose the cell splitting and group splitting algorithm, and also the fairness scheme on the basis of the nonblocking characteristics for issuing appropriate copy number depending on the number of Input cell in demand. We evaluate the performance of the proposed schemes in terms of the throughput, cell loss rate and cell delay.