• Journal of the Korean Society of Hazard Mitigation
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• v.8 no.6
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• pp.61-66
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• 2008

In railroad operation, turnout is the device designed to provide very critical functions of moving the train to the neighboring rail. It's the only movable section among the rail and track equipment, which has a complicated structure and as rapid movement between the wheel and rail during operation is unavoidable, the safety and the vibration caused by the impact load of the passing train becomes always the major concern. Response to rail vibration tends to vary depending on physical properties of the rail, rail base and the ground, making it difficult to estimate the quantitative outcome through the measurement. Thus, experimental or empirical approach, rather than an analytic method, has been more commonly employed to deal with the ground vibration. To predict the vibration of the turnout, an experimental value and the measured values are applied in parallel to the factors with a high degree of uncertainty. This study hence was intended to compare and analyze the vibration values measured at the crossing part of manganese turnout by type of train and turnout and distance, as well as predict the intensity of vibration generated at the crossing part of manganese turnout when tilting train accelerates.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.347-356
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• 2009

Precise branch prediction is a critical factor in the IPC Improvement of modern microprocessor architectures. In addition to the branch prediction accuracy, branch prediction delay have a profound impact on overall system performance as well. However, it tends to be overlooked when the architects design the branch predictor. To tolerate branch prediction delay, this paper proposes Early Start Prediction (ESP) technique. The proposed solution dynamically identifies the start instruction of basic block, called as Basic Block Start Address (BB_SA), and the solution uses BB_SA when predicting the branch direction, instead of branch instruction address itself. The performance of the proposed scheme can be further improved by combining short interval hiding technique between BB_SA and branch instruction. The simulation result shows that the proposed solution hides prediction latency, with providing same level of prediction accuracy compared to the conventional predictors. Furthermore, the combination with short interval hiding technique provides a substantial IPC improvement of up to 10.1%, and the IPC is actually same with ideal branch predictor, regardless of branch predictor configurations, such as clock frequency, delay model, and PHT size.

• The KIPS Transactions:PartA
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• v.19A no.2
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• pp.77-84
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• 2012

Speculative execution for improving instruction-level parallelism is widely used in high-performance processors. In the speculative execution technique, the most important factor is the accuracy of branch predictor. Unfortunately, complex branch predictors for improving the accuracy can cause serious thermal problems in 3D multicore processors. Thermal problems have negative impact on the processor performance. This paper analyzes two methods to solve the thermal problems in the branch predictor of 3D multi-core processors. First method is dynamic thermal management which turns off the execution of the branch predictor when the temperature of the branch predictor exceeds the threshold. Second method is thermal-aware branch predictor placement policy by considering each layer's temperature in 3D multi-core processors. According to our evaluation, the branch predictor placement policy shows that average temperature is $87.69^{\circ}C$, and average maximum temperature gradient is $11.17^{\circ}C$. And, dynamic thermal management shows that average temperature is $89.64^{\circ}C$ and average maximum temperature gradient is $17.62^{\circ}C$. Proposed branch predictor placement policy has superior thermal efficiency than the dynamic thermal management. In the perspective of performance, the proposed branch predictor placement policy degrades the performance by 3.61%, while the dynamic thermal management degrades the performance by 27.66%.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.1-10
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• 2009

Precise branch predictor has a profound impact on system performance in modern processor architectures. Recent works show that prediction latency as well as prediction accuracy has a critical impact on overall system performance as well. However, prediction latency tends to be overlooked. In this paper, we propose Branch Pre-Prediction policy to tolerate branch prediction latency. The proposed solution allows that branch predictor can proceed its prediction without any information from the fetch engine, separating the prediction engine from fetch stage. In addition, we propose newly modified BTE structure to support our solution. The simulation result shows that proposed solution can hide most prediction latency with still providing the same level of prediction accuracy. Furthermore, the proposed solution shows even better performance than the ideal case, that is the predictor which always takes a single cycle prediction latency. In our experiments, IPC improvement is up to 11.92% and 5.15% in average, compared to conventional predictor system.

• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.217-226
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• 2008

Branch prediction accuracy is critical for system performance in modern microprocessor architectures. The use of speculative update branch history provides substantial accuracy improvement in branch prediction. However, speculative update branch history is the information about uncommitted branch instruction and thus it may hurts program correctness, in case of miss-speculative execution. Therefore, speculative update branch history requires suitable recovery mechanisms to provide program correctness as well as performance improvement. In this paper, we propose recovery logics for speculative update branch history. The proposed solutions are recovery logics for both global history and local history. In simulation results, our solution provides performance improvement up to 5.64%. In addition, it guarantees the program correctness and almost 90% of additional hardware overhead is reduced, compared to previous works.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.25-27
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• 2001

본 논문에서는 AE32000 프로세서에 적응 가능한 효율적인 분기 예측 기법에 관하여 연구하였다. 실험결과, 내장형 응용분야에서의 비용 효율성이란 측면에, AE32000 프로세서에서는 1비트의 분기 예측기와 한 개의 엔트리를 갖는 BTB(Branch Target Buffer)를 사용하는 것이 가장 적합함을 관찰하였다. 또한, 분기 목적 주소에서 나타나는 LERI 명령을 폴딩하여 분기 손실을 줄이는 방안은, BTB와 LERI 폴딩 유닛을 사용하는 설계에서, 가져오는 성능 향상이 미미함을 확인하였다.

• Journal of the Korean Society for Railway
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• v.12 no.6
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• pp.859-864
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• 2009

When the vehicle passes through turnout, the design is required to minimize the change of lateral force. Therefore, in case the vehicle passed the through turnout, we ought to execute dynamic analysis of the interaction between the vehicle and turnout in order to make an estimate of the lateral force and the derailment coefficient on the turnout. In this paper, we established the analytical model of the vehicle and turnout and analysed running safety when the vehicle passes through turnout in order to improve running safety of the vehicle on turnout. Also, to verify the vehicle and turnout model, we analysed reaction force and running behavior between wheel and rail, and running safety of the vehicle by changing cradle part and the tongue rail when the vehicle passes through turnout.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.1-14
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• 2006

The indirect branch instruction is a most substantial obstacle in utilizing ILP of modem high performance processors. The target address of an indirect branch has the polymorphic characteristic varied dynamically, so it is very difficult to predict the accurate target address. Therefore the performance of a processor with speculative methodology is reduced significantly due to the many execution cycle delays in occurring the misprediction. We proposed the very accurate and novel indirect branch prediction scheme so called data-dependence based prediction. The predictor results in the prediction accuracy of 98.92% using 1K entries, and. 99.95% using 8K But, all of the proposed indirect predictor including our predictor has a large hardware overhead for restoring expected target addresses as well as tags for alleviating an aliasing. Hence, we propose the scheme minimizing the hardware overhead without sacrificing the prediction accuracy. Our experiment results show that the hardware is reduced about 60% without the performance loss, and about 80% sacrificing only the performance loss of 0.1% in aspect of the tag overhead. Also, in aspect of the overhead of storing target addresses, it can save the hardware about 35% without the performance loss, and about 45% sacrificing only the performance loss of 1.11%.

• Journal of Korean Society of Transportation
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• v.32 no.6
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• pp.600-614
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• 2014

This paper develops a model to forecast container volumes of all Korean seaports using a Seasonal ARIMA (Autoregressive Integrated Moving Average) technique with the quarterly data from the year of 1994 to 2010. In order to verify forecasting accuracy of the SARIMA model, this paper compares the predicted volumes resulted from the SARIMA model with the actual volumes. Also, the forecasted volumes of the SARIMA model is compared to those of an ARIMA model to demonstrate the superiority as a forecasting model. The results showed the SARIMA Model has a high level of forecasting accuracy and is superior to the ARIMA model in terms of estimation accuracy. Most of the previous research regarding the container-volume forecasting of seaports have been focussed on long-term forecasting with mainly monthly and yearly volume data. Therefore, this paper suggests a new methodology that forecasts shot-term demand with quarterly container volumes and demonstrates the superiority of the SARIMA model as a forecasting methodology.