• Journal of the Institute of Convergence Signal Processing
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• v.13 no.4
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• pp.194-200
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• 2012

In this paper we analyze the code sequence generating algorism defined on $GF(2^n)$ proposed by S.Bostas and V.Kumar[7] and derive the implementation functions of code sequence generator using Boolean functions which can map the vector space $F_2^n$ of all binary vectors of length n, to the finite field with two elements $F_2$. We find the code sequence generating boolean functions based on two kinds of the primitive polynomials of degree, n=5 and n=7 from trace function. We then design and implement the code sequence generators using these functions, and produce two code sequence groups. The two groups have the period 31 and 127 and the magnitudes of out of phase(${\tau}{\neq}0$) autocorrelation and crosscorrelation functions {-9, -1, 7} and {-17, -1, 15}, satisfying the period $L=2^n-1$ and the correlation functions $R_{ij}({\tau})=\{-2^{(n+1)/2}-1,-1,2^{(n+l)/2}-1\}$ respectively. Through these results, we confirm that the code sequence generators using boolean functions are designed and implemented correctly.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.1025-1032
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• 1998

In this paper, the PLD design tool which realizes a digital circuit as PLD, by using EDIF netlist of the digital circuit designed at OrCAD have been developed. This paper is proposed the following algorithms: JIE(Joined Information Extractor) which extracts the connecting information between both cells in order to realize the digital circuit as PLD using the EDIF netlist, FND(Feedback Node Detector) which look into whether feedback exists or not, BEG(Boolean Equation Generator) which generates a boolean equation, and so on. Also, this paper is developed auto-select function which selects the PLD element with consideration of number of I/O variables of the minimized boolean equation, and algorithm generation JEDEC file of GAL6001 and GAL6002, having a forms of EPLD which is bigger than PLD.

• Journal of the Korean Society for information Management
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• v.7 no.1
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• pp.79-95
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• 1990

A retrieval technique was defined as a technique for comparing the document representations. So this study classified retrieval technique in terms of the charactristics of the retrieved set of documents and the representations that are used. The distinction is whether the set of retrieved documents contains only documents whose representations are an exact match with the query, or a partial match with query. For a partial match, the set of retrieved document will include also those that are an exact match with the query. Boolean-logic as one of the exact match retrieval techniques is in current in most of the large operational information retrieval systems despite of its problems and limitatlons. Partial match as an alternative technique has also various problems. Existing information retrieval systems are successful in aSSisting the user whose needs are well- defined (e.g. Boolean-logic), to retrieve relevant documents but it should be successful in providing retrieval assistance to the browser whose information requirements is ill-defined.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04b
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• pp.556-558
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• 2001

전체 영상을 이용하지 않고 영상 안에 포함된 특정 객체 혹은 영역만을 이용하는 "영역에 의한 질의(query-by-region)" 방법은 내용기반 영상 검색 중 상위개념의 방법 이지만, 영상 분할의 한계, 여러개로 분할된 영역을 모두 검색하기 위한 인덱싱 문제, 유사성 측정 시 선형적으로 분리되지 않는 특징 값들에 대한 무리한 선형 조합으로 인한 검색 오류와 같은 많은 문제점을 안고 있다. 따라서 본 논문에서는 영역 기반 영상 검색 시스템인 FRIP에 대하여 영상 분할의 한계를 극복하고, 사용자의 주관성을 영상 검색에 적용하기 위해 확률적 연관성 학습 모델(MPFRL)을 유사성 측정 단계에서 적용 하였고, 아울러 검색 모델로는 기존에 일반적으로 사용되어 오던, 선형 모델을 사용하지 않고 선형 모델보다 유연한 검색 결과를 보여주는 확률적 이접 부울 모델(PDB)을 사용하였다. 또한, 검색 시간을 단축 시키기 위해, 선형 검색 방법에 부울 AND 연산자를 적용 시킴으로써, 검색 시간을 상당부분 단축 할 수 있었다. 실험 결과, 본 논문에서 제안하는 방법(MPFRL+PDB)을 사용할 경우 검색 결과가 선형 조합 보다 향상되는 것을 알 수 있었다. 아울러 사용자 피드백을 통해 사용자가 특징 가중치를 일일이 조절하지 않더라도 단순한 몇 번의 클릭만으로 사용자의 주관성을 반영하고 보다 정확한 검색 결과를 보여 줄 수 있는 시스템을 설계 할 수 있었다.

• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.391-397
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• 1994

In this paper, we have developed a PLD Designer which is a design tool for digital circuits design using PLD device. PLD designer consists of a state graphic editor to extract boolean equations from state table within 20 states of FSM and a pin map editor to assign pin map for PLD device(PAL16R4, PAL22V10, GAL16V8, etc), which is suitable for extracted boolean equations. Also pin map editor generates a necessary JEDEC file to implement PLD device by using fuse map and checksum algorithm. To verify extracted boolean equation, we have developed simulation test vector generation algorithm. The results of JEDEC files generated by PLD designer is same with the results of JEDEC files generated by PALASM.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1998.10a
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• pp.607-610
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• 1998

• Journal of the Korea Computer Industry Society
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• v.7 no.4
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• pp.293-298
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• 2006

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Bryton's co-kernel cube matrix.

• The Transactions of the Korea Information Processing Society
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• v.5 no.7
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• pp.1896-1907
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• 1998

확장된 마크흐름선도(EMFG: Extednded Mark Flow Graph)는 기존의 MFG를 개선한 그래프로서, 회로변수식에 의해 실제회로로 쉽게 구현가능하므로 이산제어시스템의 모델링과 설계 및 구현의 강력한 도구로 사용될 수 있다. 본 논문은 EMFG의 트랜지션들이 점화하는 과정 및 트랜지션들이 점화완료하였을 때 각 박스들의 마크수 변화를 부울함수식과 벡터를 사용하여 표현하였다. 또한 시스템의 상태변화를 쉽게 판단할 수 있게 하는 EMFG의 동작알고리듬을 제안하였으며, 제안된 알고리듬은 3-비트 증가계수기를 설계한 EMFG와 시간트랜지션이 포함된 가상의 EMFG에서 잘 수행되었다. EMFG의 동작이 부울함수로 해석가능해짐으로 인해 시스템의 분석 및 설계가 용이하며 컴퓨터를 이용한 자동화된 시스템의 분석과 설계가 가능하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.1
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• pp.25-28
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• 1982

A method for finding the symbolic reliability expressision of a conbinational logic circuit is presented. The evaluation of the probabilities of the outputs can be symbolically evaluated by the Boolean operation named sharp operation, provided that every input of such a circuit can be treated as random variables with values set(0, 1) and the output of a circuit can be represented by a Boolean sum of produt expression.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.25-34
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• 1981

Any logical stuckft faults in multivalued combinational circuits are analyzed using the concept of Boolean difference. The algebra employed is the implementation oriented algebra developed by Allen and Givone. All the lines in the circuit are classified into five types according to their properties. For each type, the equation that represents the complete test set is derived and proved. All the results in examples are confumed to be correct by comparing the truth tables of the normal and faulty circuits.